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/linux/drivers/media/platform/ti/omap3isp/
H A Dnoise_filter_table.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Noise filter table
14 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
15 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
16 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31,
17 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31
/linux/lib/crypto/powerpc/
H A Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
14 # Block size 16 bytes
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
[all …]
H A Dchacha-p10le-8x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
11 # 1. a += b; d ^= a; d <<<= 16;
16 # row1 = (row1 + row2), row4 = row1 xor row4, row4 rotate each word by 16
40 #include <asm/asm-offsets.h>
41 #include <asm/asm-compat.h>
52 li 16, \OFFSET
53 stvx \VRS, 16, \FRAME
57 li 16, \OFFSET
58 stxvx \VSX, 16, \FRAME
[all …]
/linux/drivers/video/fbdev/nvidia/
H A Dnv_dma.h8 |* hereby granted a nonexclusive, royalty-free copyright license to *|
11 |* Any use of this source code must include, in the user documenta- *|
19 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
21 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
23 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
24 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
33 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
35 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
42 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
43 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
[all …]
/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
45 #define MT_TX_FREE_MSDU_ID GENMASK(30, 16)
46 #define MT_TX_FREE_PAIR BIT(31)
50 #define MT_TXD0_Q_IDX GENMASK(31, 25)
52 #define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)
55 #define MT_TXD1_LONG_FORMAT BIT(31)
61 #define MT_TXD1_HDR_FORMAT GENMASK(17, 16)
67 #define MT_TXD2_FIX_RATE BIT(31)
70 #define MT_TXD2_MAX_TX_TIME GENMASK(23, 16)
83 #define MT_TXD3_SN_VALID BIT(31)
[all …]
/linux/arch/alpha/include/asm/
H A Dxor.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/asm-alpha/xor.h
5 * Optimized RAID-5 checksumming functions for alpha EV5 and EV6
52 srl $16, 6, $16 \n\
60 ldq $4,16($17) \n\
61 ldq $5,16($18) \n\
82 stq $4,16($17) \n\
93 subq $16,1,$16 \n\
98 bgt $16,2b \n\
107 srl $16, 6, $16 \n\
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
11 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
14 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
22 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
29 #define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16)
41 #define MT_RXD2_NORMAL_NON_AMPDU BIT(31)
56 #define MT_RXD2_NORMAL_SW_BIT BIT(16)
61 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
75 #define MT_RXD6_QOS_CTL GENMASK(31, 16)
[all …]
/linux/arch/powerpc/xmon/
H A Dppc-opc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ppc-opc.c -- PowerPC opcode list
3 Copyright (C) 1994-2016 Free Software Foundation, Inc.
27 inserting operands into instructions and vice-versa is kept in this
142 #define BI_MASK (0x1f << 16)
143 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
148 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
173 /* The BD field in a B form instruction when the - modifier is used.
179 /* The BD field in a B form instruction when the - modifier is used
224 /* The BO field in a B form instruction when the + or - modifier is
[all …]
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-pexp-defs.h7 * Copyright (c) 2003-2012 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 … CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16)
43 …e CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16)
44 …ne CVMX_PEXP_NPEI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16)
45 …X_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16)
46 …ne CVMX_PEXP_NPEI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16)
68 …I_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12)
92 …ne CVMX_PEXP_NPEI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16)
[all …]
/linux/arch/alpha/lib/
H A Dev6-clear_page.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-clear_page.S
17 addq $16,64,$2
18 addq $16,128,$3
20 addq $16,192,$17
21 wh64 ($16)
26 stq $31,0($16)
30 stq $31,8($16)
31 stq $31,16($16)
35 stq $31,24($16)
[all …]
H A Dclear_page.S1 /* SPDX-License-Identifier: GPL-2.0 */
20 1: stq $31,0($16)
21 stq $31,8($16)
22 stq $31,16($16)
23 stq $31,24($16)
25 stq $31,32($16)
26 stq $31,40($16)
27 stq $31,48($16)
30 stq $31,56($16)
31 addq $16,64,$16
H A Dmemset.S1 /* SPDX-License-Identifier: GPL-2.0 */
10 * This routine is "moral-ware": you are free to use it any way you wish, and
35 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
36 sll $17,16,$1 /* E1 (p-c latency, next cycle) */
38 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
39 sll $17,32,$1 /* E1 (p-c latency, next cycle) */
40 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
41 ldq_u $31,0($30) /* .. E1 */
45 addq $18,$16,$6 /* E0 */
46 bis $16,$16,$0 /* .. E1 */
[all …]
H A Dclear_user.S1 /* SPDX-License-Identifier: GPL-2.0 */
8 * We have to make sure that $0 is always up-to-date and contains the
19 .long 99b - .; \
20 lda $31, $exception-99b($31); \
36 0: EX( stq_u $31, 0($16) ) # e0 : zero one word
39 addq $16, 8, $16 # .. e1 :
46 2: EX( stq_u $31, 0($16) ) # e0 : zero four words
48 EX( stq_u $31, 8($16) ) # e0 :
50 EX( stq_u $31, 16($16) ) # e0 :
52 EX( stq_u $31, 24($16) ) # e0 :
[all …]
H A Dev6-copy_page.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-copy_page.S
13 -----------------------------
28 9 cycles but I was not able to get it to run that fast -- the initial
34 -------------------------------------
45 --------------------------------------
51 forced me to add another cycle to the inner-most kernel - up to 11
68 /* Prefetch 5 read cachelines; write-hint 10 cache lines. */
69 wh64 ($16)
70 ldl $31,0($17)
[all …]
H A Dev6-clear_user.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-clear_user.S
4 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
8 * We have to make sure that $0 is always up-to-date and contains the
16 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
18 * E - either cluster
19 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
20 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
25 * it's going to be worth the effort to hand-unroll a big loop, and use wh64.
37 .long 99b - .; \
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dregs.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)
19 #define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19)
51 #define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31)
58 #define MT_WPDMA_DEBUG_IDX GENMASK(31, 28)
105 #define MT_PSE_FC_P0_MAX_QUOTA GENMASK(27, 16)
116 #define MT_FC_RSV_COUNT_0_P1 GENMASK(27, 16)
120 #define MT_FC_SP2_Q0Q1_SRC_COUNT_Q1 GENMASK(27, 16)
129 #define MT_PSE_RTA_WRITE BIT(16)
130 #define MT_PSE_RTA_BUSY BIT(31)
[all …]
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
7 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
9 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
27 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
31 #define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16)
41 #define MT_RXD2_NORMAL_NON_AMPDU BIT(31)
56 #define MT_RXD2_NORMAL_SW_BIT BIT(16)
61 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
72 #define MT_RXV1_VHTA1_B5_B4 GENMASK(31, 30)
79 #define MT_RXV1_FRAME_MODE GENMASK(16, 15)
[all …]
/linux/drivers/ras/amd/atl/
H A Dreg_fields.h1 /* SPDX-License-Identifier: GPL-2.0 */
77 * DF4 DstFabricID [27:16]
80 * DF4p5 DstFabricID [23:16]
85 #define DF4_DST_FABRIC_ID GENMASK(27, 16)
86 #define DF4p5_DST_FABRIC_ID GENMASK(23, 16)
100 * DF3 DieIdMask [18:16]
110 #define DF3_DIE_ID_MASK GENMASK(18, 16)
161 * DF2 DramBaseAddr [31:12]
162 * DF3 DramBaseAddr [31:12]
163 * DF3p5 DramBaseAddr [31:12]
[all …]
/linux/arch/s390/kernel/
H A Dfpu.c1 // SPDX-License-Identifier: GPL-2.0
3 * In-kernel vector facility support functions
17 __vector128 *vxrs = state->vxrs; in __kernel_fpu_begin()
24 flags &= state->hdr.mask; in __kernel_fpu_begin()
26 fpu_stfpc(&state->hdr.fpc); in __kernel_fpu_begin()
35 vxrs += fpu_vstm(16, 31, vxrs); in __kernel_fpu_begin()
54 vxrs += fpu_vstm(16, 31, vxrs); in __kernel_fpu_begin()
56 vxrs += fpu_vstm(16, 23, vxrs); in __kernel_fpu_begin()
58 vxrs += fpu_vstm(24, 31, vxrs); in __kernel_fpu_begin()
65 __vector128 *vxrs = state->vxrs; in __kernel_fpu_end()
[all …]
/linux/drivers/hid/intel-thc-hid/intel-thc/
H A Dintel-thc-hw.h1 /* SPDX-License-Identifier: GPL-2.0 */
247 #define THC_CFG_DID_VID_DID GENMASK(31, 16)
269 #define THC_CFG_STS_CMD_DPE BIT(31)
273 #define THC_CFG_CC_RID_SCC GENMASK(23, 16)
274 #define THC_CFG_CC_RID_BCC GENMASK(31, 24)
278 #define THC_CFG_BIST_HTYPE_LT_CLS_HTYPE GENMASK(22, 16)
285 #define THC_CFG_BAR0_LOW_MEMBAR GENMASK(31, 15)
286 #define THC_CFG_BAR0_HI_MEMBAR GENMASK(31, 0)
289 #define THC_CFG_SID_SVID_SSID GENMASK(31, 16)
302 #define THC_CFG_MSIMC_MSINP_MSICID_MSIE BIT(16)
[all …]
/linux/drivers/net/ipa/reg/
H A Dipa_reg-v3.1.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
18 /* Bits 5-31 reserved */
40 [H_DCPH] = BIT(16),
41 /* Bits 17-31 reserved */
50 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
52 /* Bits 22-23 reserved */
54 /* Bits 25-31 reserved */
61 [MEM_BADDR] = GENMASK(31, 16),
69 /* Bits 8-31 reserved */
[all …]
H A Dipa_reg-v5.5.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
15 [MAX_PROD_PIPES] = GENMASK(23, 16),
16 [PROD_LOWEST] = GENMASK(31, 24),
38 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
39 /* Bits 17-18 reserved */
44 /* Bits 28-29 reserved */
46 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
68 [H_DCPH] = BIT(16),
83 [DRBIP] = BIT(31),
[all …]
/linux/drivers/bus/mhi/
H A Dcommon.h1 /* SPDX-License-Identifier: GPL-2.0 */
68 #define BHI_STATUS_MASK GENMASK(31, 30)
91 #define BHIE_TXVECSTATUS_STATUS_BMSK GENMASK(31, 30)
100 #define BHIE_RXVECSTATUS_STATUS_BMSK GENMASK(31, 30)
107 #define MHICFG_NHWER_MASK GENMASK(31, 24)
108 #define MHICFG_NER_MASK GENMASK(23, 16)
121 #define MHI_TRE_CMD_NOOP_DWORD1 cpu_to_le32(FIELD_PREP(GENMASK(23, 16), MHI_CMD_NOP))
126 #define MHI_TRE_CMD_RESET_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
127 FIELD_PREP(GENMASK(23, 16), \
133 #define MHI_TRE_CMD_STOP_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
[all …]
/linux/arch/arm64/tools/
H A Dsysreg1 # SPDX-License-Identifier: GPL-2.0-only
52 # NI - Not implemented
53 # IMP - Implemented
61 Field 31:0 DTRRX
65 Res0 63:31
77 Field 31 TFO
88 Res0 18:16
101 Field 31:0 DTRTX
112 Field 31:0 OPCODE
117 Field 31:0 EDECCR
[all …]
/linux/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_ethtool.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Applied Micro X-Gene SoC Ethernet Driver
40 XGENE_EXTD_STAT(tx_rx_64b_frame_cntr, TR64, 31),
41 XGENE_EXTD_STAT(tx_rx_127b_frame_cntr, TR127, 31),
42 XGENE_EXTD_STAT(tx_rx_255b_frame_cntr, TR255, 31),
43 XGENE_EXTD_STAT(tx_rx_511b_frame_cntr, TR511, 31),
44 XGENE_EXTD_STAT(tx_rx_1023b_frame_cntr, TR1K, 31),
45 XGENE_EXTD_STAT(tx_rx_1518b_frame_cntr, TRMAX, 31),
46 XGENE_EXTD_STAT(tx_rx_1522b_frame_cntr, TRMGV, 31),
47 XGENE_EXTD_STAT(rx_fcs_error_cntr, RFCS, 16),
[all …]

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