18485149cSManivannan Sadhasivam /* SPDX-License-Identifier: GPL-2.0 */
28485149cSManivannan Sadhasivam /*
38485149cSManivannan Sadhasivam * Copyright (c) 2022, Linaro Ltd.
48485149cSManivannan Sadhasivam *
58485149cSManivannan Sadhasivam */
68485149cSManivannan Sadhasivam
78485149cSManivannan Sadhasivam #ifndef _MHI_COMMON_H
88485149cSManivannan Sadhasivam #define _MHI_COMMON_H
98485149cSManivannan Sadhasivam
108485149cSManivannan Sadhasivam #include <linux/bitfield.h>
118485149cSManivannan Sadhasivam #include <linux/mhi.h>
128485149cSManivannan Sadhasivam
138485149cSManivannan Sadhasivam /* MHI registers */
148485149cSManivannan Sadhasivam #define MHIREGLEN 0x00
158485149cSManivannan Sadhasivam #define MHIVER 0x08
168485149cSManivannan Sadhasivam #define MHICFG 0x10
178485149cSManivannan Sadhasivam #define CHDBOFF 0x18
188485149cSManivannan Sadhasivam #define ERDBOFF 0x20
198485149cSManivannan Sadhasivam #define BHIOFF 0x28
208485149cSManivannan Sadhasivam #define BHIEOFF 0x2c
218485149cSManivannan Sadhasivam #define DEBUGOFF 0x30
228485149cSManivannan Sadhasivam #define MHICTRL 0x38
238485149cSManivannan Sadhasivam #define MHISTATUS 0x48
248485149cSManivannan Sadhasivam #define CCABAP_LOWER 0x58
258485149cSManivannan Sadhasivam #define CCABAP_HIGHER 0x5c
268485149cSManivannan Sadhasivam #define ECABAP_LOWER 0x60
278485149cSManivannan Sadhasivam #define ECABAP_HIGHER 0x64
288485149cSManivannan Sadhasivam #define CRCBAP_LOWER 0x68
298485149cSManivannan Sadhasivam #define CRCBAP_HIGHER 0x6c
308485149cSManivannan Sadhasivam #define CRDB_LOWER 0x70
318485149cSManivannan Sadhasivam #define CRDB_HIGHER 0x74
328485149cSManivannan Sadhasivam #define MHICTRLBASE_LOWER 0x80
338485149cSManivannan Sadhasivam #define MHICTRLBASE_HIGHER 0x84
348485149cSManivannan Sadhasivam #define MHICTRLLIMIT_LOWER 0x88
358485149cSManivannan Sadhasivam #define MHICTRLLIMIT_HIGHER 0x8c
368485149cSManivannan Sadhasivam #define MHIDATABASE_LOWER 0x98
378485149cSManivannan Sadhasivam #define MHIDATABASE_HIGHER 0x9c
388485149cSManivannan Sadhasivam #define MHIDATALIMIT_LOWER 0xa0
398485149cSManivannan Sadhasivam #define MHIDATALIMIT_HIGHER 0xa4
408485149cSManivannan Sadhasivam
418485149cSManivannan Sadhasivam /* MHI BHI registers */
428485149cSManivannan Sadhasivam #define BHI_BHIVERSION_MINOR 0x00
438485149cSManivannan Sadhasivam #define BHI_BHIVERSION_MAJOR 0x04
448485149cSManivannan Sadhasivam #define BHI_IMGADDR_LOW 0x08
458485149cSManivannan Sadhasivam #define BHI_IMGADDR_HIGH 0x0c
468485149cSManivannan Sadhasivam #define BHI_IMGSIZE 0x10
478485149cSManivannan Sadhasivam #define BHI_RSVD1 0x14
488485149cSManivannan Sadhasivam #define BHI_IMGTXDB 0x18
498485149cSManivannan Sadhasivam #define BHI_RSVD2 0x1c
508485149cSManivannan Sadhasivam #define BHI_INTVEC 0x20
518485149cSManivannan Sadhasivam #define BHI_RSVD3 0x24
528485149cSManivannan Sadhasivam #define BHI_EXECENV 0x28
538485149cSManivannan Sadhasivam #define BHI_STATUS 0x2c
548485149cSManivannan Sadhasivam #define BHI_ERRCODE 0x30
558485149cSManivannan Sadhasivam #define BHI_ERRDBG1 0x34
568485149cSManivannan Sadhasivam #define BHI_ERRDBG2 0x38
578485149cSManivannan Sadhasivam #define BHI_ERRDBG3 0x3c
588485149cSManivannan Sadhasivam #define BHI_SERIALNU 0x40
598485149cSManivannan Sadhasivam #define BHI_SBLANTIROLLVER 0x44
608485149cSManivannan Sadhasivam #define BHI_NUMSEG 0x48
618485149cSManivannan Sadhasivam #define BHI_MSMHWID(n) (0x4c + (0x4 * (n)))
628485149cSManivannan Sadhasivam #define BHI_OEMPKHASH(n) (0x64 + (0x4 * (n)))
638485149cSManivannan Sadhasivam #define BHI_RSVD5 0xc4
648485149cSManivannan Sadhasivam
658485149cSManivannan Sadhasivam /* BHI register bits */
668485149cSManivannan Sadhasivam #define BHI_TXDB_SEQNUM_BMSK GENMASK(29, 0)
678485149cSManivannan Sadhasivam #define BHI_TXDB_SEQNUM_SHFT 0
688485149cSManivannan Sadhasivam #define BHI_STATUS_MASK GENMASK(31, 30)
698485149cSManivannan Sadhasivam #define BHI_STATUS_ERROR 0x03
708485149cSManivannan Sadhasivam #define BHI_STATUS_SUCCESS 0x02
718485149cSManivannan Sadhasivam #define BHI_STATUS_RESET 0x00
728485149cSManivannan Sadhasivam
738485149cSManivannan Sadhasivam /* MHI BHIE registers */
748485149cSManivannan Sadhasivam #define BHIE_MSMSOCID_OFFS 0x00
758485149cSManivannan Sadhasivam #define BHIE_TXVECADDR_LOW_OFFS 0x2c
768485149cSManivannan Sadhasivam #define BHIE_TXVECADDR_HIGH_OFFS 0x30
778485149cSManivannan Sadhasivam #define BHIE_TXVECSIZE_OFFS 0x34
788485149cSManivannan Sadhasivam #define BHIE_TXVECDB_OFFS 0x3c
798485149cSManivannan Sadhasivam #define BHIE_TXVECSTATUS_OFFS 0x44
808485149cSManivannan Sadhasivam #define BHIE_RXVECADDR_LOW_OFFS 0x60
818485149cSManivannan Sadhasivam #define BHIE_RXVECADDR_HIGH_OFFS 0x64
828485149cSManivannan Sadhasivam #define BHIE_RXVECSIZE_OFFS 0x68
838485149cSManivannan Sadhasivam #define BHIE_RXVECDB_OFFS 0x70
848485149cSManivannan Sadhasivam #define BHIE_RXVECSTATUS_OFFS 0x78
858485149cSManivannan Sadhasivam
868485149cSManivannan Sadhasivam /* BHIE register bits */
878485149cSManivannan Sadhasivam #define BHIE_TXVECDB_SEQNUM_BMSK GENMASK(29, 0)
888485149cSManivannan Sadhasivam #define BHIE_TXVECDB_SEQNUM_SHFT 0
898485149cSManivannan Sadhasivam #define BHIE_TXVECSTATUS_SEQNUM_BMSK GENMASK(29, 0)
908485149cSManivannan Sadhasivam #define BHIE_TXVECSTATUS_SEQNUM_SHFT 0
918485149cSManivannan Sadhasivam #define BHIE_TXVECSTATUS_STATUS_BMSK GENMASK(31, 30)
928485149cSManivannan Sadhasivam #define BHIE_TXVECSTATUS_STATUS_SHFT 30
938485149cSManivannan Sadhasivam #define BHIE_TXVECSTATUS_STATUS_RESET 0x00
948485149cSManivannan Sadhasivam #define BHIE_TXVECSTATUS_STATUS_XFER_COMPL 0x02
958485149cSManivannan Sadhasivam #define BHIE_TXVECSTATUS_STATUS_ERROR 0x03
968485149cSManivannan Sadhasivam #define BHIE_RXVECDB_SEQNUM_BMSK GENMASK(29, 0)
978485149cSManivannan Sadhasivam #define BHIE_RXVECDB_SEQNUM_SHFT 0
988485149cSManivannan Sadhasivam #define BHIE_RXVECSTATUS_SEQNUM_BMSK GENMASK(29, 0)
998485149cSManivannan Sadhasivam #define BHIE_RXVECSTATUS_SEQNUM_SHFT 0
1008485149cSManivannan Sadhasivam #define BHIE_RXVECSTATUS_STATUS_BMSK GENMASK(31, 30)
1018485149cSManivannan Sadhasivam #define BHIE_RXVECSTATUS_STATUS_SHFT 30
1028485149cSManivannan Sadhasivam #define BHIE_RXVECSTATUS_STATUS_RESET 0x00
1038485149cSManivannan Sadhasivam #define BHIE_RXVECSTATUS_STATUS_XFER_COMPL 0x02
1048485149cSManivannan Sadhasivam #define BHIE_RXVECSTATUS_STATUS_ERROR 0x03
1058485149cSManivannan Sadhasivam
1068485149cSManivannan Sadhasivam /* MHI register bits */
1078485149cSManivannan Sadhasivam #define MHICFG_NHWER_MASK GENMASK(31, 24)
1088485149cSManivannan Sadhasivam #define MHICFG_NER_MASK GENMASK(23, 16)
1098485149cSManivannan Sadhasivam #define MHICFG_NHWCH_MASK GENMASK(15, 8)
1108485149cSManivannan Sadhasivam #define MHICFG_NCH_MASK GENMASK(7, 0)
1118485149cSManivannan Sadhasivam #define MHICTRL_MHISTATE_MASK GENMASK(15, 8)
1128485149cSManivannan Sadhasivam #define MHICTRL_RESET_MASK BIT(1)
1138485149cSManivannan Sadhasivam #define MHISTATUS_MHISTATE_MASK GENMASK(15, 8)
1148485149cSManivannan Sadhasivam #define MHISTATUS_SYSERR_MASK BIT(2)
1158485149cSManivannan Sadhasivam #define MHISTATUS_READY_MASK BIT(0)
1168485149cSManivannan Sadhasivam
1178485149cSManivannan Sadhasivam /* Command Ring Element macros */
1188485149cSManivannan Sadhasivam /* No operation command */
1198485149cSManivannan Sadhasivam #define MHI_TRE_CMD_NOOP_PTR 0
1208485149cSManivannan Sadhasivam #define MHI_TRE_CMD_NOOP_DWORD0 0
1218485149cSManivannan Sadhasivam #define MHI_TRE_CMD_NOOP_DWORD1 cpu_to_le32(FIELD_PREP(GENMASK(23, 16), MHI_CMD_NOP))
1228485149cSManivannan Sadhasivam
1238485149cSManivannan Sadhasivam /* Channel reset command */
1248485149cSManivannan Sadhasivam #define MHI_TRE_CMD_RESET_PTR 0
1258485149cSManivannan Sadhasivam #define MHI_TRE_CMD_RESET_DWORD0 0
1268485149cSManivannan Sadhasivam #define MHI_TRE_CMD_RESET_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
1278485149cSManivannan Sadhasivam FIELD_PREP(GENMASK(23, 16), \
1288485149cSManivannan Sadhasivam MHI_CMD_RESET_CHAN))
1298485149cSManivannan Sadhasivam
1308485149cSManivannan Sadhasivam /* Channel stop command */
1318485149cSManivannan Sadhasivam #define MHI_TRE_CMD_STOP_PTR 0
1328485149cSManivannan Sadhasivam #define MHI_TRE_CMD_STOP_DWORD0 0
1338485149cSManivannan Sadhasivam #define MHI_TRE_CMD_STOP_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
1348485149cSManivannan Sadhasivam FIELD_PREP(GENMASK(23, 16), \
1358485149cSManivannan Sadhasivam MHI_CMD_STOP_CHAN))
1368485149cSManivannan Sadhasivam
1378485149cSManivannan Sadhasivam /* Channel start command */
1388485149cSManivannan Sadhasivam #define MHI_TRE_CMD_START_PTR 0
1398485149cSManivannan Sadhasivam #define MHI_TRE_CMD_START_DWORD0 0
1408485149cSManivannan Sadhasivam #define MHI_TRE_CMD_START_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
1418485149cSManivannan Sadhasivam FIELD_PREP(GENMASK(23, 16), \
1428485149cSManivannan Sadhasivam MHI_CMD_START_CHAN))
1438485149cSManivannan Sadhasivam
1448485149cSManivannan Sadhasivam #define MHI_TRE_GET_DWORD(tre, word) le32_to_cpu((tre)->dword[(word)])
1458485149cSManivannan Sadhasivam #define MHI_TRE_GET_CMD_CHID(tre) FIELD_GET(GENMASK(31, 24), MHI_TRE_GET_DWORD(tre, 1))
1468485149cSManivannan Sadhasivam #define MHI_TRE_GET_CMD_TYPE(tre) FIELD_GET(GENMASK(23, 16), MHI_TRE_GET_DWORD(tre, 1))
1478485149cSManivannan Sadhasivam
1488485149cSManivannan Sadhasivam /* Event descriptor macros */
1498485149cSManivannan Sadhasivam #define MHI_TRE_EV_PTR(ptr) cpu_to_le64(ptr)
1508485149cSManivannan Sadhasivam #define MHI_TRE_EV_DWORD0(code, len) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), code) | \
1518485149cSManivannan Sadhasivam FIELD_PREP(GENMASK(15, 0), len))
1528485149cSManivannan Sadhasivam #define MHI_TRE_EV_DWORD1(chid, type) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
1538485149cSManivannan Sadhasivam FIELD_PREP(GENMASK(23, 16), type))
1548485149cSManivannan Sadhasivam #define MHI_TRE_GET_EV_PTR(tre) le64_to_cpu((tre)->ptr)
1558485149cSManivannan Sadhasivam #define MHI_TRE_GET_EV_CODE(tre) FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 0)))
1568485149cSManivannan Sadhasivam #define MHI_TRE_GET_EV_LEN(tre) FIELD_GET(GENMASK(15, 0), (MHI_TRE_GET_DWORD(tre, 0)))
1578485149cSManivannan Sadhasivam #define MHI_TRE_GET_EV_CHID(tre) FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 1)))
1588485149cSManivannan Sadhasivam #define MHI_TRE_GET_EV_TYPE(tre) FIELD_GET(GENMASK(23, 16), (MHI_TRE_GET_DWORD(tre, 1)))
1598485149cSManivannan Sadhasivam #define MHI_TRE_GET_EV_STATE(tre) FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 0)))
1608485149cSManivannan Sadhasivam #define MHI_TRE_GET_EV_EXECENV(tre) FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 0)))
1618485149cSManivannan Sadhasivam #define MHI_TRE_GET_EV_SEQ(tre) MHI_TRE_GET_DWORD(tre, 0)
1628485149cSManivannan Sadhasivam #define MHI_TRE_GET_EV_TIME(tre) MHI_TRE_GET_EV_PTR(tre)
1638485149cSManivannan Sadhasivam #define MHI_TRE_GET_EV_COOKIE(tre) lower_32_bits(MHI_TRE_GET_EV_PTR(tre))
1648485149cSManivannan Sadhasivam #define MHI_TRE_GET_EV_VEID(tre) FIELD_GET(GENMASK(23, 16), (MHI_TRE_GET_DWORD(tre, 0)))
1658485149cSManivannan Sadhasivam #define MHI_TRE_GET_EV_LINKSPEED(tre) FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 1)))
1668485149cSManivannan Sadhasivam #define MHI_TRE_GET_EV_LINKWIDTH(tre) FIELD_GET(GENMASK(7, 0), (MHI_TRE_GET_DWORD(tre, 0)))
1678485149cSManivannan Sadhasivam
168961aeb68SManivannan Sadhasivam /* State change event */
169961aeb68SManivannan Sadhasivam #define MHI_SC_EV_PTR 0
170961aeb68SManivannan Sadhasivam #define MHI_SC_EV_DWORD0(state) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), state))
171961aeb68SManivannan Sadhasivam #define MHI_SC_EV_DWORD1(type) cpu_to_le32(FIELD_PREP(GENMASK(23, 16), type))
172961aeb68SManivannan Sadhasivam
173961aeb68SManivannan Sadhasivam /* EE event */
174961aeb68SManivannan Sadhasivam #define MHI_EE_EV_PTR 0
175961aeb68SManivannan Sadhasivam #define MHI_EE_EV_DWORD0(ee) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), ee))
176961aeb68SManivannan Sadhasivam #define MHI_EE_EV_DWORD1(type) cpu_to_le32(FIELD_PREP(GENMASK(23, 16), type))
177961aeb68SManivannan Sadhasivam
178961aeb68SManivannan Sadhasivam
179961aeb68SManivannan Sadhasivam /* Command Completion event */
180961aeb68SManivannan Sadhasivam #define MHI_CC_EV_PTR(ptr) cpu_to_le64(ptr)
181961aeb68SManivannan Sadhasivam #define MHI_CC_EV_DWORD0(code) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), code))
182961aeb68SManivannan Sadhasivam #define MHI_CC_EV_DWORD1(type) cpu_to_le32(FIELD_PREP(GENMASK(23, 16), type))
183961aeb68SManivannan Sadhasivam
1848485149cSManivannan Sadhasivam /* Transfer descriptor macros */
1858485149cSManivannan Sadhasivam #define MHI_TRE_DATA_PTR(ptr) cpu_to_le64(ptr)
1868485149cSManivannan Sadhasivam #define MHI_TRE_DATA_DWORD0(len) cpu_to_le32(FIELD_PREP(GENMASK(15, 0), len))
1878485149cSManivannan Sadhasivam #define MHI_TRE_TYPE_TRANSFER 2
1888485149cSManivannan Sadhasivam #define MHI_TRE_DATA_DWORD1(bei, ieot, ieob, chain) cpu_to_le32(FIELD_PREP(GENMASK(23, 16), \
1898485149cSManivannan Sadhasivam MHI_TRE_TYPE_TRANSFER) | \
1908485149cSManivannan Sadhasivam FIELD_PREP(BIT(10), bei) | \
1918485149cSManivannan Sadhasivam FIELD_PREP(BIT(9), ieot) | \
1928485149cSManivannan Sadhasivam FIELD_PREP(BIT(8), ieob) | \
1938485149cSManivannan Sadhasivam FIELD_PREP(BIT(0), chain))
194961aeb68SManivannan Sadhasivam #define MHI_TRE_DATA_GET_PTR(tre) le64_to_cpu((tre)->ptr)
195961aeb68SManivannan Sadhasivam #define MHI_TRE_DATA_GET_LEN(tre) FIELD_GET(GENMASK(15, 0), MHI_TRE_GET_DWORD(tre, 0))
196961aeb68SManivannan Sadhasivam #define MHI_TRE_DATA_GET_CHAIN(tre) (!!(FIELD_GET(BIT(0), MHI_TRE_GET_DWORD(tre, 1))))
197961aeb68SManivannan Sadhasivam #define MHI_TRE_DATA_GET_IEOB(tre) (!!(FIELD_GET(BIT(8), MHI_TRE_GET_DWORD(tre, 1))))
198961aeb68SManivannan Sadhasivam #define MHI_TRE_DATA_GET_IEOT(tre) (!!(FIELD_GET(BIT(9), MHI_TRE_GET_DWORD(tre, 1))))
199961aeb68SManivannan Sadhasivam #define MHI_TRE_DATA_GET_BEI(tre) (!!(FIELD_GET(BIT(10), MHI_TRE_GET_DWORD(tre, 1))))
2008485149cSManivannan Sadhasivam
2018485149cSManivannan Sadhasivam /* RSC transfer descriptor macros */
2028485149cSManivannan Sadhasivam #define MHI_RSCTRE_DATA_PTR(ptr, len) cpu_to_le64(FIELD_PREP(GENMASK(64, 48), len) | ptr)
2038485149cSManivannan Sadhasivam #define MHI_RSCTRE_DATA_DWORD0(cookie) cpu_to_le32(cookie)
2048485149cSManivannan Sadhasivam #define MHI_RSCTRE_DATA_DWORD1 cpu_to_le32(FIELD_PREP(GENMASK(23, 16), \
2058485149cSManivannan Sadhasivam MHI_PKT_TYPE_COALESCING))
2068485149cSManivannan Sadhasivam
2078485149cSManivannan Sadhasivam enum mhi_pkt_type {
2088485149cSManivannan Sadhasivam MHI_PKT_TYPE_INVALID = 0x0,
2098485149cSManivannan Sadhasivam MHI_PKT_TYPE_NOOP_CMD = 0x1,
2108485149cSManivannan Sadhasivam MHI_PKT_TYPE_TRANSFER = 0x2,
2118485149cSManivannan Sadhasivam MHI_PKT_TYPE_COALESCING = 0x8,
2128485149cSManivannan Sadhasivam MHI_PKT_TYPE_RESET_CHAN_CMD = 0x10,
2138485149cSManivannan Sadhasivam MHI_PKT_TYPE_STOP_CHAN_CMD = 0x11,
2148485149cSManivannan Sadhasivam MHI_PKT_TYPE_START_CHAN_CMD = 0x12,
2158485149cSManivannan Sadhasivam MHI_PKT_TYPE_STATE_CHANGE_EVENT = 0x20,
2168485149cSManivannan Sadhasivam MHI_PKT_TYPE_CMD_COMPLETION_EVENT = 0x21,
2178485149cSManivannan Sadhasivam MHI_PKT_TYPE_TX_EVENT = 0x22,
2188485149cSManivannan Sadhasivam MHI_PKT_TYPE_RSC_TX_EVENT = 0x28,
2198485149cSManivannan Sadhasivam MHI_PKT_TYPE_EE_EVENT = 0x40,
2208485149cSManivannan Sadhasivam MHI_PKT_TYPE_TSYNC_EVENT = 0x48,
2218485149cSManivannan Sadhasivam MHI_PKT_TYPE_BW_REQ_EVENT = 0x50,
2228485149cSManivannan Sadhasivam MHI_PKT_TYPE_STALE_EVENT, /* internal event */
2238485149cSManivannan Sadhasivam };
2248485149cSManivannan Sadhasivam
2258485149cSManivannan Sadhasivam /* MHI transfer completion events */
2268485149cSManivannan Sadhasivam enum mhi_ev_ccs {
2278485149cSManivannan Sadhasivam MHI_EV_CC_INVALID = 0x0,
2288485149cSManivannan Sadhasivam MHI_EV_CC_SUCCESS = 0x1,
2298485149cSManivannan Sadhasivam MHI_EV_CC_EOT = 0x2, /* End of transfer event */
2308485149cSManivannan Sadhasivam MHI_EV_CC_OVERFLOW = 0x3,
2318485149cSManivannan Sadhasivam MHI_EV_CC_EOB = 0x4, /* End of block event */
2328485149cSManivannan Sadhasivam MHI_EV_CC_OOB = 0x5, /* Out of block event */
2338485149cSManivannan Sadhasivam MHI_EV_CC_DB_MODE = 0x6,
2348485149cSManivannan Sadhasivam MHI_EV_CC_UNDEFINED_ERR = 0x10,
2358485149cSManivannan Sadhasivam MHI_EV_CC_BAD_TRE = 0x11,
2368485149cSManivannan Sadhasivam };
2378485149cSManivannan Sadhasivam
2388485149cSManivannan Sadhasivam /* Channel state */
2398485149cSManivannan Sadhasivam enum mhi_ch_state {
2408485149cSManivannan Sadhasivam MHI_CH_STATE_DISABLED,
2418485149cSManivannan Sadhasivam MHI_CH_STATE_ENABLED,
2428485149cSManivannan Sadhasivam MHI_CH_STATE_RUNNING,
2438485149cSManivannan Sadhasivam MHI_CH_STATE_SUSPENDED,
2448485149cSManivannan Sadhasivam MHI_CH_STATE_STOP,
2458485149cSManivannan Sadhasivam MHI_CH_STATE_ERROR,
2468485149cSManivannan Sadhasivam };
2478485149cSManivannan Sadhasivam
2488485149cSManivannan Sadhasivam enum mhi_cmd_type {
2498485149cSManivannan Sadhasivam MHI_CMD_NOP = 1,
2508485149cSManivannan Sadhasivam MHI_CMD_RESET_CHAN = 16,
2518485149cSManivannan Sadhasivam MHI_CMD_STOP_CHAN = 17,
2528485149cSManivannan Sadhasivam MHI_CMD_START_CHAN = 18,
2538485149cSManivannan Sadhasivam };
2548485149cSManivannan Sadhasivam
2558485149cSManivannan Sadhasivam #define EV_CTX_RESERVED_MASK GENMASK(7, 0)
2568485149cSManivannan Sadhasivam #define EV_CTX_INTMODC_MASK GENMASK(15, 8)
2578485149cSManivannan Sadhasivam #define EV_CTX_INTMODT_MASK GENMASK(31, 16)
2588485149cSManivannan Sadhasivam struct mhi_event_ctxt {
2598485149cSManivannan Sadhasivam __le32 intmod;
2608485149cSManivannan Sadhasivam __le32 ertype;
2618485149cSManivannan Sadhasivam __le32 msivec;
2628485149cSManivannan Sadhasivam
2638485149cSManivannan Sadhasivam __le64 rbase __packed __aligned(4);
2648485149cSManivannan Sadhasivam __le64 rlen __packed __aligned(4);
2658485149cSManivannan Sadhasivam __le64 rp __packed __aligned(4);
2668485149cSManivannan Sadhasivam __le64 wp __packed __aligned(4);
2678485149cSManivannan Sadhasivam };
2688485149cSManivannan Sadhasivam
2698485149cSManivannan Sadhasivam #define CHAN_CTX_CHSTATE_MASK GENMASK(7, 0)
2708485149cSManivannan Sadhasivam #define CHAN_CTX_BRSTMODE_MASK GENMASK(9, 8)
2718485149cSManivannan Sadhasivam #define CHAN_CTX_POLLCFG_MASK GENMASK(15, 10)
2728485149cSManivannan Sadhasivam #define CHAN_CTX_RESERVED_MASK GENMASK(31, 16)
2738485149cSManivannan Sadhasivam struct mhi_chan_ctxt {
2748485149cSManivannan Sadhasivam __le32 chcfg;
2758485149cSManivannan Sadhasivam __le32 chtype;
2768485149cSManivannan Sadhasivam __le32 erindex;
2778485149cSManivannan Sadhasivam
2788485149cSManivannan Sadhasivam __le64 rbase __packed __aligned(4);
2798485149cSManivannan Sadhasivam __le64 rlen __packed __aligned(4);
2808485149cSManivannan Sadhasivam __le64 rp __packed __aligned(4);
2818485149cSManivannan Sadhasivam __le64 wp __packed __aligned(4);
2828485149cSManivannan Sadhasivam };
2838485149cSManivannan Sadhasivam
2848485149cSManivannan Sadhasivam struct mhi_cmd_ctxt {
2858485149cSManivannan Sadhasivam __le32 reserved0;
2868485149cSManivannan Sadhasivam __le32 reserved1;
2878485149cSManivannan Sadhasivam __le32 reserved2;
2888485149cSManivannan Sadhasivam
2898485149cSManivannan Sadhasivam __le64 rbase __packed __aligned(4);
2908485149cSManivannan Sadhasivam __le64 rlen __packed __aligned(4);
2918485149cSManivannan Sadhasivam __le64 rp __packed __aligned(4);
2928485149cSManivannan Sadhasivam __le64 wp __packed __aligned(4);
2938485149cSManivannan Sadhasivam };
2948485149cSManivannan Sadhasivam
2958485149cSManivannan Sadhasivam struct mhi_ring_element {
2968485149cSManivannan Sadhasivam __le64 ptr;
2978485149cSManivannan Sadhasivam __le32 dword[2];
2988485149cSManivannan Sadhasivam };
2998485149cSManivannan Sadhasivam
300*ceeb64f4SKrishna chaitanya chundru #define MHI_STATE_LIST \
301*ceeb64f4SKrishna chaitanya chundru mhi_state(RESET, "RESET") \
302*ceeb64f4SKrishna chaitanya chundru mhi_state(READY, "READY") \
303*ceeb64f4SKrishna chaitanya chundru mhi_state(M0, "M0") \
304*ceeb64f4SKrishna chaitanya chundru mhi_state(M1, "M1") \
305*ceeb64f4SKrishna chaitanya chundru mhi_state(M2, "M2") \
306*ceeb64f4SKrishna chaitanya chundru mhi_state(M3, "M3") \
307*ceeb64f4SKrishna chaitanya chundru mhi_state(M3_FAST, "M3_FAST") \
308*ceeb64f4SKrishna chaitanya chundru mhi_state(BHI, "BHI") \
309*ceeb64f4SKrishna chaitanya chundru mhi_state_end(SYS_ERR, "SYS ERROR")
310*ceeb64f4SKrishna chaitanya chundru
311*ceeb64f4SKrishna chaitanya chundru #undef mhi_state
312*ceeb64f4SKrishna chaitanya chundru #undef mhi_state_end
313*ceeb64f4SKrishna chaitanya chundru
314*ceeb64f4SKrishna chaitanya chundru #define mhi_state(a, b) case MHI_STATE_##a: return b;
315*ceeb64f4SKrishna chaitanya chundru #define mhi_state_end(a, b) case MHI_STATE_##a: return b;
316*ceeb64f4SKrishna chaitanya chundru
mhi_state_str(enum mhi_state state)3173a1b8e28SManivannan Sadhasivam static inline const char *mhi_state_str(enum mhi_state state)
3183a1b8e28SManivannan Sadhasivam {
3193a1b8e28SManivannan Sadhasivam switch (state) {
320*ceeb64f4SKrishna chaitanya chundru MHI_STATE_LIST
3213a1b8e28SManivannan Sadhasivam default:
3223a1b8e28SManivannan Sadhasivam return "Unknown state";
3233a1b8e28SManivannan Sadhasivam }
324*ceeb64f4SKrishna chaitanya chundru }
3258485149cSManivannan Sadhasivam
3268485149cSManivannan Sadhasivam #endif /* _MHI_COMMON_H */
327