Lines Matching +full:16 +full:- +full:31
1 /* SPDX-License-Identifier: GPL-2.0 */
77 * DF4 DstFabricID [27:16]
80 * DF4p5 DstFabricID [23:16]
85 #define DF4_DST_FABRIC_ID GENMASK(27, 16)
86 #define DF4p5_DST_FABRIC_ID GENMASK(23, 16)
100 * DF3 DieIdMask [18:16]
110 #define DF3_DIE_ID_MASK GENMASK(18, 16)
161 * DF2 DramBaseAddr [31:12]
162 * DF3 DramBaseAddr [31:12]
163 * DF3p5 DramBaseAddr [31:12]
171 #define DF2_BASE_ADDR GENMASK(31, 12)
183 * DF2 DramHoleBase [31:24]
184 * DF3 DramHoleBase [31:24]
185 * DF3p5 DramHoleBase [31:24]
188 * DF4 DramHoleBase [31:24]
189 * DF4p5 DramHoleBase [31:24]
191 #define DF_DRAM_HOLE_BASE_MASK GENMASK(31, 24)
202 * DF2 DramLimitAddr [31:12]
203 * DF3 DramLimitAddr [31:12]
204 * DF3p5 DramLimitAddr [31:12]
212 #define DF2_DRAM_LIMIT_ADDR GENMASK(31, 12)
264 * DF2 HiAddrOffset [31:20]
265 * DF3 HiAddrOffset [31:12]
266 * DF3p5 HiAddrOffset [31:12]
271 * MI300 HiAddrOffset [31:1]
273 #define DF2_HI_ADDR_OFFSET GENMASK(31, 20)
274 #define DF3_HI_ADDR_OFFSET GENMASK(31, 12)
277 #define DF4_HI_ADDR_OFFSET GENMASK(31, 1)
427 * D18F2x90 [Non-power-of-2 channel Configuration Register for COH_ST DRAM Address Maps]
467 * DF4 MinorRevision [23:16]
468 * DF4p5 MinorRevision [23:16]
470 #define DF_MINOR_REVISION GENMASK(23, 16)
483 * DF3 NodeIdMask [25:16]
486 * DF3p5 NodeIdMask [31:16]
489 * DF4 NodeIdMask [31:16]
490 * DF4p5 NodeIdMask [31:16]
492 #define DF3_NODE_ID_MASK GENMASK(25, 16)
493 #define DF4_NODE_ID_MASK GENMASK(31, 16)
567 * DF2 SocketIdMask [23:16]
573 * DF3p5 SocketIdMask [31:16]
576 * DF4 SocketIdMask [31:16]
577 * DF4p5 SocketIdMask [31:16]
579 #define DF2_SOCKET_ID_MASK GENMASK(23, 16)
581 #define DF4_SOCKET_ID_MASK GENMASK(31, 16)
592 * DF2 SocketIdShift [31:28]
604 #define DF2_SOCKET_ID_SHIFT GENMASK(31, 28)