| /linux/lib/crypto/ |
| H A D | blake2s-generic.c | 20 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
21 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
22 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
23 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
24 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
25 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
26 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
27 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
28 { 6, 15, 14, 9, 11, 3, 0, 8, 12, 2, 13, 7, 1, 4, 10, 5 },
29 { 10, 2, 8, 4, 7, 6, 1, 5, 15, 11, 9, 14, 3, 12, 13, 0 },
[all …]
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| /linux/crypto/ |
| H A D | blake2b_generic.c | 26 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
27 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
28 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
29 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
30 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
31 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
32 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
33 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
34 { 6, 15, 14, 9, 11, 3, 0, 8, 12, 2, 13, 7, 1, 4, 10, 5 },
35 { 10, 2, 8, 4, 7, 6, 1, 5, 15, 11, 9, 14, 3, 12, 13, 0 },
[all …]
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| /linux/arch/arm/crypto/ |
| H A D | blake2s-core.S | 113 // Execute one round of BLAKE2s by updating the state matrix v[0..15]. v[0..9]
115 // spilling v[8..9], then to v[9..15], then to the message block. r10-r12 and
132 // (v[0], v[4], v[8], v[12]) and (v[1], v[5], v[9], v[13]).
133 __ldrd r10, r11, sp, 16 // load v[12] and v[13]
140 // (v[2], v[6], v[10], v[14]) and (v[3], v[7], v[11], v[15]).
141 __ldrd r8, r9, sp, 8 // load v[10] and v[11]
142 __ldrd r10, r11, sp, 24 // load v[14] and v[15]
145 str r10, [sp, #24] // store v[14]
146 // v[10], v[11], and v[15] are used below, so no need to store them yet.
152 // (v[0], v[5], v[10], v[15]) and (v[1], v[6], v[11], v[12]).
[all …]
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| H A D | blake2b-neon-core.S | 63 // Execute one round of BLAKE2b by updating the state matrix v[0..15] in the
73 // (v[0], v[4], v[8], v[12]), (v[1], v[5], v[9], v[13]),
74 // (v[2], v[6], v[10], v[14]), and (v[3], v[7], v[11], v[15]).
145 // (v[0], v[5], v[10], v[15]), (v[1], v[6], v[11], v[12]),
146 // (v[2], v[7], v[8], v[13]), and (v[3], v[4], v[9], v[14]).
274 // 'v'. Fortunately, there are exactly enough NEON registers to fit the
285 veor q6, q6, q14 // v[12..13] = IV[4..5] ^ t[0..1]
287 veor q7, q7, q15 // v[14..15] = IV[6..7] ^ f[0..1]
295 _blake2b_round 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
296 _blake2b_round 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3
[all …]
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| /linux/arch/arm64/crypto/ |
| H A D | sha512-ce-core.S | 15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
85 ld1 {v\rc1\().2d}, [x4], #16
87 add v5.2d, v\rc0\().2d, v\in0\().2d
88 ext v6.16b, v\i2\().16b, v\i3\().16b, #8
90 ext v7.16b, v\i1\().16b, v\i2\().16b, #8
91 add v\i3\().2d, v\i3\().2d, v5.2d
93 ext v5.16b, v\in3\().16b, v\in4\().16b, #8
94 sha512su0 v\in0\().2d, v\in1\().2d
98 sha512su1 v\in0\().2d, v\in2\().2d, v5.2d
100 add v\i4\().2d, v\i1\().2d, v\i3\().2d
[all …]
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| /linux/drivers/media/platform/verisilicon/ |
| H A D | rockchip_vpu2_hw_h264_dec.c | 28 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
30 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
31 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
32 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
33 #define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) argument
34 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
36 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
37 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
39 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
40 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
[all …]
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| H A D | hantro_g1_regs.h | 21 #define G1_REG_INTERRUPT_DEC_BUFFER_INT BIT(14)
61 #define G1_REG_DEC_CTRL0_FILTERING_DIS BIT(14)
89 #define G1_REG_DEC_CTRL2_CH_QP_OFFSET2(x) (((x) & 0x1f) << 14)
148 #define G1_REG_DEC_CTRL4_PQINDEX(x) (((x) & 0x1f) << 14)
180 #define G1_REG_DEC_CTRL5_REF_DIST_BWD(x) (((x) & 0x1f) << 14)
181 #define G1_REG_DEC_CTRL5_LOOP_FILT_LIMIT(x) (((x) & 0xf) << 14)
190 #define G1_REG_DEC_CTRL5_RV_FWD_SCALE(x) (((x) & 0x3fff) << 14)
197 #define G1_REG_DEC_CTRL6_REFIDX0_ACTIVE(x) (((x) & 0x1f) << 14)
242 #define G1_REG_REF_PIC_MB_ADJ_1(x) (((x) & 0x7f) << 14)
294 #define G1_REG_REF_BUF_CTRL_REFBU_PICID(x) (((x) & 0x1f) << 14)
[all …]
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| H A D | hantro_g1_mpeg2_dec.c | 19 #define G1_REG_REFER0_BASE G1_SWREG(14)
25 #define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
26 #define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0) argument
27 #define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0) argument
28 #define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0) argument
29 #define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0) argument
30 #define G1_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(19) : 0) argument
31 #define G1_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(18) : 0) argument
32 #define G1_REG_DEC_LATENCY(v) (((v) << 11) & GENMASK(16, 11)) argument
33 #define G1_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(10) : 0) argument
[all …]
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| /linux/arch/alpha/kernel/ |
| H A D | entry.S | 156 .cfi_rel_offset $14, 40
167 .cfi_restore $14
204 stq $14, 40($sp)
211 .cfi_rel_offset $14, 40
224 ldq $14, 40($sp)
232 .cfi_restore $14
270 stq $14, 112($sp)
298 .cfi_rel_offset $14, 14*8
329 ldq $14, 112($sp)
357 .cfi_restore $14
[all …]
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| /linux/drivers/media/platform/nxp/ |
| H A D | imx-pxp.h | 19 #define BF_PXP_CTRL_SFTRST(v) \ argument
20 (((v) << 31) & BM_PXP_CTRL_SFTRST)
22 #define BF_PXP_CTRL_CLKGATE(v) \ argument
23 (((v) << 30) & BM_PXP_CTRL_CLKGATE)
25 #define BF_PXP_CTRL_RSVD4(v) \ argument
26 (((v) << 29) & BM_PXP_CTRL_RSVD4)
28 #define BF_PXP_CTRL_EN_REPEAT(v) \ argument
29 (((v) << 28) & BM_PXP_CTRL_EN_REPEAT)
31 #define BF_PXP_CTRL_ENABLE_ROTATE1(v) \ argument
32 (((v) << 27) & BM_PXP_CTRL_ENABLE_ROTATE1)
[all …]
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| /linux/kernel/locking/ |
| H A D | lockdep_proc.c | 38 static void *l_next(struct seq_file *m, void *v, loff_t *pos) in l_next() argument
40 struct lock_class *class = v; in l_next()
56 static void l_stop(struct seq_file *m, void *v) in l_stop() argument
77 static int l_show(struct seq_file *m, void *v) in l_show() argument
79 struct lock_class *class = v; in l_show()
84 if (v == lock_classes) in l_show()
139 static void *lc_next(struct seq_file *m, void *v, loff_t *pos) in lc_next() argument
145 static void lc_stop(struct seq_file *m, void *v) in lc_stop() argument
149 static int lc_show(struct seq_file *m, void *v) in lc_show() argument
151 struct lock_chain *chain = v; in lc_show()
[all …]
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| /linux/drivers/staging/media/sunxi/cedrus/ |
| H A D | cedrus_regs.h | 13 #define SHIFT_AND_MASK_BITS(v, h, l) \ argument
14 (((unsigned long)(v) << (l)) & GENMASK(h, l))
104 #define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \ argument
105 ((v) ? BIT(7) : 0)
106 #define VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT(v) \ argument
107 ((v) ? BIT(6) : 0)
108 #define VE_DEC_MPEG_MP12HDR_CONCEALMENT_MOTION_VECTORS(v) \ argument
109 ((v) ? BIT(5) : 0)
110 #define VE_DEC_MPEG_MP12HDR_Q_SCALE_TYPE(v) \ argument
111 ((v) ? BIT(4) : 0)
[all …]
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| /linux/drivers/media/platform/sunxi/sun6i-csi/ |
| H A D | sun6i_csi_reg.h | 18 #define SUN6I_CSI_EN_PTN_CYCLE(v) (((v) << 16) & GENMASK(23, 16)) argument
29 #define SUN6I_CSI_IF_CFG_FIELD_DT_PCLK_SHIFT(v) (((v) << 24) & GENMASK(27, 24)) argument
41 #define SUN6I_CSI_IF_CFG_FIELD_DT_FIELD_VSYNC (0 << 14)
42 #define SUN6I_CSI_IF_CFG_FIELD_DT_FIELD (1 << 14)
43 #define SUN6I_CSI_IF_CFG_FIELD_DT_VSYNC (2 << 14)
57 #define SUN6I_CSI_CAP_MASK(v) (((v) << 2) & GENMASK(5, 2)) argument
70 #define SUN6I_CSI_CH_CFG_PAD_VAL(v) (((v) << 24) & GENMASK(31, 24)) argument
71 #define SUN6I_CSI_CH_CFG_INPUT_FMT(v) (((v) << 20) & GENMASK(23, 20)) argument
72 #define SUN6I_CSI_CH_CFG_OUTPUT_FMT(v) (((v) << 16) & GENMASK(19, 16)) argument
78 #define SUN6I_CSI_CH_CFG_INPUT_YUV_SEQ(v) (((v) << 8) & GENMASK(9, 8)) argument
[all …]
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| /linux/lib/ |
| H A D | bitfield_kunit.c | 11 #define CHECK_ENC_GET_U(tp, v, field, res) do { \ argument
15 _res = u##tp##_encode_bits(v, field); \
17 "u" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != " #res "\n", \
20 u##tp##_get_bits(_res, field) != v); \
24 #define CHECK_ENC_GET_LE(tp, v, field, res) do { \ argument
28 _res = le##tp##_encode_bits(v, field); \
31 "le" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != 0x%llx",\
35 le##tp##_get_bits(_res, field) != v);\
39 #define CHECK_ENC_GET_BE(tp, v, field, res) do { \ argument
43 _res = be##tp##_encode_bits(v, field); \
[all …]
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| /linux/arch/x86/include/asm/ |
| H A D | perf_event_p4.h | 40 #define P4_ESCR_EVENT(v) ((v) << P4_ESCR_EVENT_SHIFT) argument
41 #define P4_ESCR_EMASK(v) ((v) << P4_ESCR_EVENTMASK_SHIFT) argument
42 #define P4_ESCR_TAG(v) ((v) << P4_ESCR_TAG_SHIFT) argument
62 #define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT) argument
63 #define P4_CCCR_ESEL(v) ((v) << P4_CCCR_ESCR_SELECT_SHIFT) argument
81 #define p4_config_pack_escr(v) (((u64)(v)) << 32) argument
82 #define p4_config_pack_cccr(v) (((u64)(v)) & 0xffffffffULL) argument
83 #define p4_config_unpack_escr(v) (((u64)(v)) >> 32) argument
84 #define p4_config_unpack_cccr(v) (((u64)(v)) & 0xffffffffULL) argument
86 #define p4_config_unpack_emask(v) \ argument
[all …]
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| /linux/drivers/video/fbdev/ |
| H A D | valkyriefb.h | 11 * vmode 10 changed by Steven Borley <sjb@salix.demon.co.uk>, 14 mai 2000
102 { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
108 /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
118 { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
119 /* I interpolated the V=69.71 from the vmode 14 and old 15
126 /* Register values for 1024x768, 60Hz mode (14) */
128 14,
129 { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
138 { 23, 42, 3 }, /* pixel clock = 57.07MHz for V=74.27Hz */
146 { 17, 27, 3 }, /* pixel clock = 49.63MHz for V=71.66Hz */
[all …]
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| /linux/drivers/gpu/drm/exynos/ |
| H A D | regs-scaler.h | 55 * 0 60 64 68 6c 140 144 148 14c
159 #define SCALER_INT_EN_ILLEGAL_DST_Y_BASE (1 << 14)
187 #define SCALER_INT_STATUS_ILLEGAL_DST_Y_BASE (1 << 14)
206 #define SCALER_SRC_CFG_SET_BYTE_SWAP(v) SCALER_SET(v, 6, 5) argument
208 #define SCALER_SRC_CFG_SET_COLOR_FORMAT(v) SCALER_SET(v, 4, 0) argument
221 #define SCALER_RGBA8888 14
232 #define SCALER_SRC_SPAN_SET_C_SPAN(v) SCALER_SET(v, 29, 16) argument
234 #define SCALER_SRC_SPAN_SET_Y_SPAN(v) SCALER_SET(v, 13, 0) argument
238 #define SCALER_SRC_Y_POS_SET_YH_POS(v) SCALER_SET(v, 31, 16) argument
240 #define SCALER_SRC_Y_POS_SET_YV_POS(v) SCALER_SET(v, 15, 0) argument
[all …]
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| /linux/drivers/mtd/nand/raw/gpmi-nand/ |
| H A D | bch-regs.h | 30 #define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) \ argument
31 (((v) << BP_BCH_FLASH0LAYOUT0_NBLOCKS) & BM_BCH_FLASH0LAYOUT0_NBLOCKS)
35 #define BF_BCH_FLASH0LAYOUT0_META_SIZE(v) \ argument
36 (((v) << BP_BCH_FLASH0LAYOUT0_META_SIZE)\
43 #define BF_BCH_FLASH0LAYOUT0_ECC0(v, x) \ argument
45 ? (((v) << MX6Q_BP_BCH_FLASH0LAYOUT0_ECC0) \
47 : (((v) << BP_BCH_FLASH0LAYOUT0_ECC0) \
54 #define BF_BCH_FLASH0LAYOUT0_GF(v, x) \ argument
55 ((GPMI_IS_MX6(x) && ((v) == 14)) \
66 #define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v, x) \ argument
[all …]
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| /linux/drivers/video/backlight/ |
| H A D | ltv350qv.h | 28 #define LTV_NMD (1 << 14)
51 #define LTV_HSPL_ACTIVE_LOW (0 << 14)
52 #define LTV_HSPL_ACTIVE_HIGH (1 << 14)
67 #define LTV_NW_INV_FRAME (0 << 14)
68 #define LTV_NW_INV_1LINE (1 << 14)
69 #define LTV_NW_INV_2LINE (2 << 14)
81 #define LTV_VCOM_DISABLE (1 << 14)
89 #define LTV_VCOML_VOLTAGE(x) (((x) & 0x001f) << 8) /* 0=1V, 31=-1V */
90 #define LTV_VCOMH_VOLTAGE(x) (((x) & 0x001f) << 0) /* 0=3V, 31=4.5V */
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| /linux/sound/soc/mxs/ |
| H A D | mxs-saif.h | 20 #define BF_SAIF_CTRL_BITCLK_MULT_RATE(v) \ argument
21 (((v) << 27) & BM_SAIF_CTRL_BITCLK_MULT_RATE)
30 #define BF_SAIF_CTRL_DMAWAIT_COUNT(v) \ argument
31 (((v) << 16) & BM_SAIF_CTRL_DMAWAIT_COUNT)
32 #define BP_SAIF_CTRL_CHANNEL_NUM_SELECT 14
34 #define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v) \ argument
35 (((v) << 14) & BM_SAIF_CTRL_CHANNEL_NUM_SELECT)
44 #define BF_SAIF_CTRL_WORD_LENGTH(v) \ argument
45 (((v) << 4) & BM_SAIF_CTRL_WORD_LENGTH)
55 #define BF_SAIF_STAT_RSRVD2(v) \ argument
[all …]
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| /linux/drivers/i3c/master/mipi-i3c-hci/ |
| H A D | cmd_v1.c | 27 #define CMD_A0_DEV_COUNT(v) FIELD_PREP(W0_MASK(29, 26), v) argument
28 #define CMD_A0_DEV_INDEX(v) FIELD_PREP(W0_MASK(20, 16), v) argument
29 #define CMD_A0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v) argument
30 #define CMD_A0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v) argument
38 #define CMD_I1_DATA_BYTE_4(v) FIELD_PREP(W1_MASK(63, 56), v) argument
39 #define CMD_I1_DATA_BYTE_3(v) FIELD_PREP(W1_MASK(55, 48), v) argument
40 #define CMD_I1_DATA_BYTE_2(v) FIELD_PREP(W1_MASK(47, 40), v) argument
41 #define CMD_I1_DATA_BYTE_1(v) FIELD_PREP(W1_MASK(39, 32), v) argument
42 #define CMD_I1_DEF_BYTE(v) FIELD_PREP(W1_MASK(39, 32), v) argument
46 #define CMD_I0_MODE(v) FIELD_PREP(W0_MASK(28, 26), v) argument
[all …]
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| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | nvidia,tegra20-sdhci.yaml | 113 description: Specify drive strength calibration offsets for 1.8 V
119 automatic calibration times out on a 1.8 V signaling mode.
123 description: Specify drive strength calibration offsets for 3.3 V
129 automatic calibration times out on a 3.3 V signaling mode.
141 description: Specify drive strength calibration offsets for 1.8 V
147 automatic calibration times out on a 1.8 V signaling mode.
151 description: Specify drive strength calibration offsets for 3.3 V
164 automatic calibration times out on a 3.3 V signaling mode.
175 nvidia,only-1-8v:
177 operates at a 1.8 V fixed I/O voltage.
[all …]
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| /linux/drivers/gpu/host1x/hw/ |
| H A D | opcodes.h | 52 u32 v = host1x_uclass_indoff_indbe_f(0xf) in host1x_class_host_indoff_reg_write() local
56 v |= host1x_uclass_indoff_autoinc_f(1); in host1x_class_host_indoff_reg_write()
57 return v; in host1x_class_host_indoff_reg_write()
63 u32 v = host1x_uclass_indoff_indmodid_f(mod_id) in host1x_class_host_indoff_reg_read() local
67 v |= host1x_uclass_indoff_autoinc_f(1); in host1x_class_host_indoff_reg_read()
68 return v; in host1x_class_host_indoff_reg_read()
120 return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count; in host1x_opcode_gather_incr()
140 return (14 << 28) | (0 << 24) | mlock; in host1x_opcode_acquire_mlock()
145 return (14 << 28) | (1 << 24) | mlock; in host1x_opcode_release_mlock()
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| /linux/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/ |
| H A D | sun8i_a83t_mipi_csi2_reg.h | 38 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_CRC_ERR_VC2 BIT(14)
63 #define SUN8I_A83T_MIPI_CSI2_INT_STA1_DT_ERR_VC2 BIT(14)
93 #define SUN8I_A83T_MIPI_CSI2_INT_MSK0_CRC_ERR_VC2 BIT(14)
110 #define SUN8I_A83T_MIPI_CSI2_INT_MSK1_DT_ERR_VC2 BIT(14)
134 #define SUN8I_A83T_MIPI_CSI2_CFG_SYNC_DLY_CYCLE(v) (((v) << 18) & \ argument
136 #define SUN8I_A83T_MIPI_CSI2_CFG_N_CHANNEL(v) ((((v) - 1) << 16) & \ argument
138 #define SUN8I_A83T_MIPI_CSI2_CFG_N_LANE(v) ((((v) - 1) << 4) & \ argument
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| /linux/include/linux/ |
| H A D | inet.h | 12 * $Id: Space.c,v 0.8.4.5 1992/12/12 19:25:04 bir7 Exp $
13 * $Id: arp.c,v 0.8.4.6 1993/01/28 22:30:00 bir7 Exp $
14 * $Id: arp.h,v 0.8.4.6 1993/01/28 22:30:00 bir7 Exp $
15 * $Id: dev.c,v 0.8.4.13 1993/01/23 18:00:11 bir7 Exp $
16 * $Id: dev.h,v 0.8.4.7 1993/01/23 18:00:11 bir7 Exp $
17 * $Id: eth.c,v 0.8.4.4 1993/01/22 23:21:38 bir7 Exp $
18 * $Id: eth.h,v 0.8.4.1 1992/11/10 00:17:18 bir7 Exp $
19 * $Id: icmp.c,v 0.8.4.9 1993/01/23 18:00:11 bir7 Exp $
20 * $Id: icmp.h,v 0.8.4.2 1992/11/15 14:55:30 bir7 Exp $
21 * $Id: ip.c,v 0.8.4.8 1992/12/12 19:25:04 bir7 Exp $
[all …]
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