Lines Matching +full:14 +full:v
21 #define G1_REG_INTERRUPT_DEC_BUFFER_INT BIT(14)
61 #define G1_REG_DEC_CTRL0_FILTERING_DIS BIT(14)
89 #define G1_REG_DEC_CTRL2_CH_QP_OFFSET2(x) (((x) & 0x1f) << 14)
148 #define G1_REG_DEC_CTRL4_PQINDEX(x) (((x) & 0x1f) << 14)
180 #define G1_REG_DEC_CTRL5_REF_DIST_BWD(x) (((x) & 0x1f) << 14)
181 #define G1_REG_DEC_CTRL5_LOOP_FILT_LIMIT(x) (((x) & 0xf) << 14)
190 #define G1_REG_DEC_CTRL5_RV_FWD_SCALE(x) (((x) & 0x3fff) << 14)
197 #define G1_REG_DEC_CTRL6_REFIDX0_ACTIVE(x) (((x) & 0x1f) << 14)
242 #define G1_REG_REF_PIC_MB_ADJ_1(x) (((x) & 0x7f) << 14)
294 #define G1_REG_REF_BUF_CTRL_REFBU_PICID(x) (((x) & 0x1f) << 14)
301 #define G1_REG_REF_BUF_CTRL2_REFBU2_PICID(x) (((x) & 0x1f) << 14)
313 #define G1_REG_PP_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24))
314 #define G1_REG_PP_AXI_WR_ID(v) (((v) << 16) & GENMASK(23, 16))
315 #define G1_REG_PP_INSWAP32_E(v) ((v) ? BIT(10) : 0)
316 #define G1_REG_PP_DATA_DISC_E(v) ((v) ? BIT(9) : 0)
317 #define G1_REG_PP_CLK_GATE_E(v) ((v) ? BIT(8) : 0)
318 #define G1_REG_PP_IN_ENDIAN(v) ((v) ? BIT(7) : 0)
319 #define G1_REG_PP_OUT_ENDIAN(v) ((v) ? BIT(6) : 0)
320 #define G1_REG_PP_OUTSWAP32_E(v) ((v) ? BIT(5) : 0)
321 #define G1_REG_PP_MAX_BURST(v) (((v) << 0) & GENMASK(4, 0))
332 #define G1_REG_PP_INPUT_SIZE_HEIGHT(v) (((v) << 9) & GENMASK(16, 9))
333 #define G1_REG_PP_INPUT_SIZE_WIDTH(v) (((v) << 0) & GENMASK(8, 0))
335 #define G1_REG_PP_PADD_R(v) (((v) << 23) & GENMASK(27, 23))
336 #define G1_REG_PP_PADD_G(v) (((v) << 18) & GENMASK(22, 18))
337 #define G1_REG_PP_RANGEMAP_Y(v) ((v) ? BIT(31) : 0)
338 #define G1_REG_PP_RANGEMAP_C(v) ((v) ? BIT(30) : 0)
339 #define G1_REG_PP_YCBCR_RANGE(v) ((v) ? BIT(29) : 0)
340 #define G1_REG_PP_RGB_16(v) ((v) ? BIT(28) : 0)
342 #define G1_REG_PP_PADD_B(v) (((v) << 18) & GENMASK(22, 18))
347 #define G1_REG_PP_CONTROL_IN_FMT(v) (((v) << 29) & GENMASK(31, 29))
348 #define G1_REG_PP_CONTROL_OUT_FMT(v) (((v) << 26) & GENMASK(28, 26))
349 #define G1_REG_PP_CONTROL_OUT_HEIGHT(v) (((v) << 15) & GENMASK(25, 15))
350 #define G1_REG_PP_CONTROL_OUT_WIDTH(v) (((v) << 4) & GENMASK(14, 4))
352 #define G1_REG_PP_ORIG_WIDTH(v) (((v) << 23) & GENMASK(31, 23))