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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/MCTargetDesc/
H A DLoongArchFixupKinds.h1 //===- LoongArchFixupKinds.h - LoongArch Specific Fixup Entries -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
26 // 16-bit fixup corresponding to %b16(foo) for instructions like bne.
28 // 21-bit fixup corresponding to %b21(foo) for instructions like bnez.
30 // 26-bit fixup corresponding to %b26(foo)/%plt(foo) for instructions b/bl.
32 // 20-bit fixup corresponding to %abs_hi20(foo) for instruction lu12i.w.
34 // 12-bit fixup corresponding to %abs_lo12(foo) for instruction ori.
36 // 20-bit fixup corresponding to %abs64_lo20(foo) for instruction lu32i.d.
38 // 12-bit fixup corresponding to %abs_hi12(foo) for instruction lu52i.d.
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/freebsd/sys/contrib/dev/rtw88/
H A Drtw8821c.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
19 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -4
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H A Dtx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
27 #define RTW_TX_DESC_W0_BMC BIT(24)
28 #define RTW_TX_DESC_W0_LS BIT(26)
29 #define RTW_TX_DESC_W0_DISQSELSEQ BIT(31)
30 #define RTW_TX_DESC_W1_QSEL GENMASK(12, 8)
34 #define RTW_TX_DESC_W1_MORE_DATA BIT(29)
35 #define RTW_TX_DESC_W2_AGG_EN BIT(12)
36 #define RTW_TX_DESC_W2_SPE_RPT BIT(19)
38 #define RTW_TX_DESC_W2_BT_NULL BIT(23)
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H A Drtw8822c.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
161 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
179 #define BIT_LDOE25_PON BIT(0)
196 #define BITS_SUBTUNE GENMASK(15, 12)
207 #define BIT_PT_OPT BIT(21)
210 #define BIT_PATH_EN BIT(31)
212 #define BIT_DIS_SHARERX_TXGAT BIT(27)
213 #define BIT_3WIRE_TX_EN BIT(0)
214 #define BIT_3WIRE_RX_EN BIT(1)
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/freebsd/contrib/file/magic/Magdir/
H A Dmach2 #------------------------------------------------------------
8 #------------------------------------------------------------
9 # if set, it's for the 64-bit version of the architecture
10 # yes, this is separate from the low-order magic number bit
11 # it's also separate from the "64-bit libraries" bit in the
14 # Reference: https://opensource.apple.com/source/cctools/cctools-949.0.1/
15 # include/mach-o/loader.h
17 0 name mach-o-cpu
20 # 32-bit ABIs.
36 >>>4 belong&0x00ffffff 12 uvaxIII
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H A Daudio2 #------------------------------------------------------------------------------
12 >12 belong 1 8-bit ISDN mu-law,
14 >12 belong 2 8-bit linear PCM [REF-PCM],
16 >12 belong 3 16-bit linear PCM,
18 >12 belong 4 24-bit linear PCM,
20 >12 belong 5 32-bit linear PCM,
22 >12 belong 6 32-bit IEEE floating point,
24 >12 belong 7 64-bit IEEE floating point,
26 >12 belong 8 Fragmented sample data,
27 >12 belong 10 DSP program,
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H A Dplaydate2 #------------------------------------------------------------------------------
8 # https://github.com/jaames/playdate-reverse-engineering
16 >12 belong&0x80 0x80 (compressed)
19 >12 belong&0x80 0x00 (uncompressed)
25 >12 belong&0x80 0x80 (compressed)
29 >12 belong&0x80 0x00 (uncompressed)
35 >12 belong&0x80 0x80 (compressed)
36 >12 belong&0x80 0x00 (uncompressed)
40 >12 lelong&0xffffff x %d Hz,
41 >15 byte 0 unsigned, 8-bit PCM, 1 channel
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVFixupKinds.h1 //===-- RISCVFixupKinds.h - RISC-V Specific Fixup Entries ------
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/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dtda1997x.txt1 Device-Tree bindings for the NXP TDA1997x HDMI receiver
6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
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/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
37 #define MT_TX_FREE_COUNT GENMASK(12, 0)
41 #define MT_TX_FREE_PAIR BIT(31)
50 #define MT_TXD1_LONG_FORMAT BIT(31)
51 #define MT_TXD1_TGID BIT(30)
53 #define MT_TXD1_AMSDU BIT(23)
58 #define MT_TXD1_ETH_802_3 BIT(15)
59 #define MT_TXD1_VTA BIT(10)
62 #define MT_TXD2_FIX_RATE BIT(31)
63 #define MT_TXD2_FIXED_RATE BIT(30)
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H A Dmt76_connac3_mac.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_RXD0_MESH BIT(18)
29 #define MT_RXD0_MHCP BIT(19)
31 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
32 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
40 #define MT_RXD1_NORMAL_GROUP_1 BIT(16)
41 #define MT_RXD1_NORMAL_GROUP_2 BIT(17)
42 #define MT_RXD1_NORMAL_GROUP_3 BIT(18)
43 #define MT_RXD1_NORMAL_GROUP_4 BIT(19)
44 #define MT_RXD1_NORMAL_GROUP_5 BIT(20)
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7603/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
34 #define MT_RXD1_NORMAL_BEACON_UC BIT(5)
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H A Dregs.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
25 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
26 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
27 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
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/freebsd/sys/contrib/dev/rtw89/
H A Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
9 #define B_AX_AUTOLOAD_SUS BIT(5)
13 #define B_AX_PWC_EV2EF_B15 BIT(15)
14 #define B_AX_PWC_EV2EF_B14 BIT(14)
15 #define B_AX_ISO_EB2CORE BIT(
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H A Dfw.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
26 #define RTW89_C2HREG_HDR_ACK BIT(7)
28 #define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12)
38 #define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7)
40 #define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12)
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/freebsd/sys/amd64/vmm/amd/
H A Damdvi_priv.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
37 #define BIT(n) (1ULL << (n)) macro
38 /* Return value of bits[n:m] where n and (n >= ) m are bit positions. */
40 ((1 << (((n) - (m)) + 1)) - 1))
45 #define AMDVI_PCI_CAP_IOTLB BIT(0) /* IOTLB is supported. */
46 #define AMDVI_PCI_CAP_HT BIT(1) /* HyperTransport tunnel support. */
47 #define AMDVI_PCI_CAP_NPCACHE BIT(2) /* Not present page cached. */
48 #define AMDVI_PCI_CAP_EFR BIT(3) /* Extended features. */
49 #define AMDVI_PCI_CAP_EXT BIT(4) /* Miscellaneous information reg. */
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/freebsd/sys/dev/sfxge/common/
H A Defx_regs.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2016 Solarflare Communications Inc.
48 * FR_AB_EE_VPD_CFG0_REG_SF(128bit):
54 * FR_AB_EE_VPD_CFG0_REG(128bit):
94 * FR_AB_PCIE_SD_CTL0123_REG_SF(128bit):
100 * FR_AB_PCIE_SD_CTL0123_REG(128bit):
162 * FR_AB_PCIE_SD_CTL45_REG_SF(128bit):
168 * FR_AB_PCIE_SD_CTL45_REG(128bit):
198 #define FRF_AB_PCIE_DEQ3_LBN 12
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H A Defx_regs_pci.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2016 Solarflare Communications Inc.
41 * PC_VEND_ID_REG(16bit):
52 * PC_DEV_ID_REG(16bit):
63 * PC_CMD_REG(16bit):
94 * PC_STAT_REG(16bit):
107 #define PCRF_AZ_GOT_TABRT_LBN 12
125 * PC_REV_ID_REG(8bit):
136 * PC_CC_REG(24bit):
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dmc13xxx.txt4 - compatible : Should be "fsl,mc13783" or "fsl,mc13892"
7 - fsl,mc13xxx-uses-adc : Indicate the ADC is being used
8 - fsl,mc13xxx-uses-codec : Indicate the Audio Codec is being used
9 - fsl,mc13xxx-uses-rtc : Indicate the RTC is being used
10 - fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used
12 Sub-nodes:
13 - codec: Contain the Audio Codec node.
14 - adc-port: Contain PMIC SSI port number used for ADC.
15 - dac-port: Contain PMIC SSI port number used for DAC.
16 - leds : Contain the led nodes and initial register values in property
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMFixupKinds.h1 //===-- ARMFixupKinds.h - ARM Specific Fixup Entries -------
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrFormats.td1 //===- ARCInstrFormats.td - ARC Instruction Formats --------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
21 "\n return isUInt<"#BSz#">(N->getSExtValue());"> {
27 "\n return isInt<"#BSz#">(N->getSExtValue());"> {
31 // e.g. s3 field may encode the signed integers values -1 .. 6
34 "\n return isInt<"#BSz#">(N->getSExtValue());"> {
64 class ExtMode<bit mode, string instSfx, string asmSfx> {
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsV.td1 //===-- RISCVInstrFormatsV.td - RISC-V V Instruction Formats -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the RISC-V V extension instruction formats.
11 //===----------------------------------------------------------------------===//
65 let Inst{29-20} = vtypei{9-0};
66 let Inst{19-15} = uimm;
67 let Inst{14-12} = OPCFG.Value;
68 let Inst{11-7} = rd;
69 let Inst{6-0} = OPC_OP_V.Value;
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/freebsd/sys/arm64/rockchip/
H A Drk_pinctrl.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
77 uint32_t bit; member
114 #define RK_PINCTRL_LOCK(_sc) mtx_lock_spin(&(_sc)->mtx)
115 #define RK_PINCTRL_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->mtx)
116 #define RK_PINCTRL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED)
131 .bit = _bit, \
181 /* 5,0 - Empty */
184 /* 5,3 - Empty */
188 /* 6,3 - Empty */
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/freebsd/contrib/netbsd-tests/include/
H A Dd_bitstring_27.out17 12 1 16 2
34 be: 0 -1 000000000000000000000000000
35 is: 0 -1 000000000000000000000000000
59 12 0
76 be: 0 -1 000000000000000000000000000
77 is: 0 -1 000000000000000000000000000
84 be: 0 -1 000000000000000000000000000
85 is: 0 -1 000000000000000000000000000
88 be: 0 -1 000000000000000000000000000
89 is: 0 -1 000000000000000000000000000
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