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/linux/Documentation/devicetree/bindings/net/
H A Dmicrochip,lan8650.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip LAN8650/1 10BASE-T1S MACPHY Ethernet Controllers
10 - Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
14 PHY to enable 10BASE‑T1S networks. The Ethernet Media Access Controller
15 (MAC) module implements a 10 Mbps half duplex Ethernet MAC, compatible
16 with the IEEE 802.3 standard and a 10BASE-T1S physical layer transceiver
18 the MAC-PHY is specified in the OPEN Alliance 10BASE-T1x MACPHY Serial
22 - $ref: /schemas/net/ethernet-controller.yaml#
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/linux/drivers/net/phy/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
40 Adds support for a set of LED trigger events per-PHY. Link
44 logical-or of all the link speed ones.
69 Currently tested with mpc866ads and mpc8349e-mitx.
92 These are C45 PHYs 10G that require all a generic firmware.
121 - ADIN1200 - Robust,Industrial, Low Power 10/100 Ethernet PHY
122 - ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
130 - ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY
144 Currently supports the Asix Electronics PHY found in the X-Surf 100
153 found in the X-Surf 100 AX88796B package.
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H A Dmdio-open-alliance.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mdio-open-alliance.h - definition of OPEN Alliance SIG standard registers
13 /* Open Alliance TC14 (10BASE-T1S) registers */
H A Dphy-c45.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include "mdio-open-alliance.h"
12 #include "phylib-internal.h"
15 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities
22 if (phydev->pma_extable == -ENODATA) { in genphy_c45_baset1_able()
27 phydev->pma_extable = val; in genphy_c45_baset1_able()
30 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); in genphy_c45_baset1_able()
34 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support
49 * genphy_c45_pma_resume - wakes up the PMA module
55 return -EOPNOTSUPP; in genphy_c45_pma_resume()
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/linux/net/ethtool/
H A Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
17 [NETIF_F_SG_BIT] = "tx-scatter-gather",
18 [NETIF_F_IP_CSUM_BIT] = "tx-checksum-ipv4",
19 [NETIF_F_HW_CSUM_BIT] = "tx-checksum-ip-generic",
20 [NETIF_F_IPV6_CSUM_BIT] = "tx-checksum-ipv6",
22 [NETIF_F_FRAGLIST_BIT] = "tx-scatter-gather-fraglist",
23 [NETIF_F_HW_VLAN_CTAG_TX_BIT] = "tx-vlan-hw-insert",
25 [NETIF_F_HW_VLAN_CTAG_RX_BIT] = "rx-vlan-hw-parse",
26 [NETIF_F_HW_VLAN_CTAG_FILTER_BIT] = "rx-vlan-filter",
27 [NETIF_F_HW_VLAN_STAG_TX_BIT] = "tx-vlan-stag-hw-insert",
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/linux/drivers/net/ethernet/microchip/lan865x/
H A Dlan865x.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Microchip's LAN865x 10BASE-T1S MAC-PHY driver
62 ret = lan865x_set_hw_macaddr_low_bytes(priv->tc6, mac); in lan865x_set_hw_macaddr()
68 ret = oa_tc6_write_register(priv->tc6, LAN865X_REG_MAC_H_SADDR1, in lan865x_set_hw_macaddr()
76 restore_ret = lan865x_set_hw_macaddr_low_bytes(priv->tc6, in lan865x_set_hw_macaddr()
77 priv->netdev->dev_addr); in lan865x_set_hw_macaddr()
99 if (ether_addr_equal(address->sa_data, netdev->dev_addr)) in lan865x_set_mac_address()
102 ret = lan865x_set_hw_macaddr(priv, address->sa_data); in lan865x_set_mac_address()
139 netdev_for_each_mc_addr(ha, priv->netdev) { in lan865x_set_specific_multicast_addr()
140 u32 bit_num = lan865x_hash(ha->addr); in lan865x_set_specific_multicast_addr()
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/linux/Documentation/networking/
H A Doa-tc6-framework.rst1 .. SPDX-License-Identifier: GPL-2.0+
4 OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface (TC6) Framework Support
8 ------------
10 The IEEE 802.3cg project defines two 10 Mbit/s PHYs operating over a
11 single pair of conductors. The 10BASE-T1L (Clause 146) is a long reach
12 PHY supporting full duplex point-to-point operation over 1 km of single
13 balanced pair of conductors. The 10BASE-T1S (Clause 147) is a short reach
14 PHY supporting full / half duplex point-to-point operation over 15 m of
21 works in conjunction with the 10BASE-T1S PHY operating in multidrop mode.
23 The aforementioned PHYs are intended to cover the low-speed / low-cost
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/linux/drivers/net/usb/
H A Dsmsc95xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2007-2008 SMSC
59 #define PHY_HWIRQ (SMSC95XX_NR_IRQS - 1)
88 struct smsc95xx_priv *pdata = dev->driver_priv; in smsc95xx_read_reg()
93 if (current != pdata->pm_task) in smsc95xx_read_reg()
102 ret = ret < 0 ? ret : -ENODATA; in smsc95xx_read_reg()
104 if (ret != -ENODEV) in smsc95xx_read_reg()
105 netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n", in smsc95xx_read_reg()
119 struct smsc95xx_priv *pdata = dev->driver_priv; in smsc95xx_write_reg()
124 if (current != pdata->pm_task) in smsc95xx_write_reg()
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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