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/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
94 mode "640x480-100"
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
[all …]
/linux/tools/testing/selftests/intel_pstate/
H A Drun.sh6 # state to the minimum supported frequency, in decrements of 100MHz. The
10 # or the requested frequency in MHz, the Actual frequency, as read from
22 #/tmp/result.3100:1:cpu MHz : 2899.980
23 #/tmp/result.3100:2:cpu MHz : 2900.000
28 # for consistency and modified to remove the extra MHz values. The result.X
65 grep MHz /proc/cpuinfo | sort -u > /tmp/result.freqs
85 # MAIN (ALL UNITS IN MHZ)
100 [ $EVALUATE_ONLY -eq 0 ] && for freq in `seq $max_freq -100 $min_freq`
103 cpupower frequency-set -g powersave --max=${freq}MHz >& /dev/null
107 [ $EVALUATE_ONLY -eq 0 ] && cpupower frequency-set -g powersave --max=${max_freq}MHz >& /dev/null
[all …]
/linux/arch/mips/jazz/
H A DKconfig7 This is a machine with a R4400 133/150 MHz CPU. To compile a Linux
18 This is a machine with a R4000 100 MHz CPU. To compile a Linux
28 This is a machine with a R4000 100 MHz CPU. To compile a Linux
/linux/drivers/media/pci/mantis/
H A Dmantis_vp3030.c33 .frequency_min = 47 * MHz,
34 .frequency_max = 862 * MHz,
36 .ref_multiplier = 6, /* 1/6 MHz */
37 .ref_divider = 100000, /* 1/6 MHz */
51 msleep(100); in vp3030_frontend_init()
53 msleep(100); in vp3030_frontend_init()
/linux/arch/powerpc/boot/dts/
H A Diss4xx-mpic.dts38 clock-frequency = <100000000>; // 100Mhz :-)
52 clock-frequency = <100000000>; // 100Mhz :-)
68 clock-frequency = <100000000>; // 100Mhz :-)
84 clock-frequency = <100000000>; // 100Mhz :-)
/linux/Documentation/admin-guide/pm/
H A Dintel-speed-select.rst154 base-frequency(MHz):2600
168 condition is met, then base frequency of 2600 MHz can be maintained. To
183 base-frequency(MHz):2800
211 This matches the base-frequency (MHz) field value displayed from the
215 To check if the average frequency is equal to the base frequency for a 100% busy
261 Which shows that the base frequency now increased from 2600 MHz at performance
262 level 0 to 2800 MHz at performance level 4. As a result, any workload, which can
263 use fewer CPUs, can see a boost of 200 MHz compared to performance level 0.
424 Specify clos min in MHz with [--min|-n]
425 Specify clos max in MHz with [--max|-m]
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dqcom,ipq4019-mdio.yaml42 - description: MDIO clock source frequency fixed to 100MHZ
53 MDC rate is feed by an external clock (fixed 100MHz) and is divider
57 To follow 802.3 standard that instruct up to 2.5MHz by default, if
59 default 1.5625Mhz is select.
/linux/Documentation/devicetree/bindings/cpu/
H A Dcpu-capacity.txt38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
105 entry-latency-us = <100>;
128 capacity-dmips-mhz = <1024>;
[all …]
/linux/arch/mips/txx9/rbtx4927/
H A Dsetup.c231 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. in rbtx4927_clock_init()
235 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5) in rbtx4927_clock_init()
236 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3) in rbtx4927_clock_init()
237 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5) in rbtx4927_clock_init()
238 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6) in rbtx4927_clock_init()
239 * i.e. S9[3]: ON (83MHz), OFF (100MHz) in rbtx4927_clock_init()
245 txx9_cpu_clock = 166666666; /* 166MHz */ in rbtx4927_clock_init()
248 txx9_cpu_clock = 200000000; /* 200MHz */ in rbtx4927_clock_init()
255 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. in rbtx4937_clock_init()
260 * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8) in rbtx4937_clock_init()
[all …]
/linux/drivers/phy/intel/
H A Dphy-intel-keembay-emmc.c59 unsigned int mhz; in keembay_emmc_phy_power() local
84 mhz = DIV_ROUND_CLOSEST(clk_get_rate(priv->emmcclk), 1000000); in keembay_emmc_phy_power()
85 if (mhz <= 200 && mhz >= 170) in keembay_emmc_phy_power()
87 else if (mhz <= 170 && mhz >= 140) in keembay_emmc_phy_power()
89 else if (mhz <= 140 && mhz >= 110) in keembay_emmc_phy_power()
91 else if (mhz <= 110 && mhz >= 80) in keembay_emmc_phy_power()
93 else if (mhz <= 80 && mhz >= 50) in keembay_emmc_phy_power()
99 if (mhz > 175) in keembay_emmc_phy_power()
100 dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz); in keembay_emmc_phy_power()
156 if (mhz == 0) in keembay_emmc_phy_power()
[all …]
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_llc.c63 /* convert DDR frequency from units of 266.6MHz to bandwidth */ in get_ia_constants()
84 * ring_freq = 2 * GT. ring_freq is in 100MHz units in calc_ia_freq()
89 /* max(2 * GT, DDR). NB: GT is 50MHz units */ in calc_ia_freq()
104 * For GPU frequencies less than 750MHz, in calc_ia_freq()
111 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); in calc_ia_freq()
/linux/drivers/cpufreq/
H A Dlongrun.c56 ((longrun_high_freq - longrun_low_freq) / 100); in longrun_get_policy()
58 ((longrun_high_freq - longrun_low_freq) / 100); in longrun_get_policy()
81 pctg_lo = pctg_hi = 100; in longrun_set_policy()
84 ((longrun_high_freq - longrun_low_freq) / 100); in longrun_set_policy()
86 ((longrun_high_freq - longrun_low_freq) / 100); in longrun_set_policy()
89 if (pctg_hi > 100) in longrun_set_policy()
90 pctg_hi = 100; in longrun_set_policy()
221 /* read out current core MHz and current perf_pctg */ in longrun_determine_freqs()
227 pr_debug("percentage is %u %%, freq is %u MHz\n", ecx, eax); in longrun_determine_freqs()
235 ebx = (((cpu_khz / 1000) * ecx) / 100); /* to MHz */ in longrun_determine_freqs()
[all …]
/linux/drivers/clk/qcom/
H A Dipq-cmn-pll.c13 * On the IPQ9574 SoC, there are three clocks with 50 MHZ and one clock
14 * with 25 MHZ which are output from the CMN PLL to Ethernet PHY (or switch),
15 * and one clock with 353 MHZ to PPE. The other fixed rate output clocks
16 * are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS
17 * with 31.25 MHZ.
19 * On the IPQ5424 SoC, there is an output clock from CMN PLL to PPE at 375 MHZ,
20 * and an output clock to NSS (network subsystem) at 300 MHZ. The other output
29 * | +-------------> eth0-50mhz
31 * -------->+ +-------------> eth1-50mhz
33 * | +-------------> eth2-50mhz
[all …]
/linux/drivers/scsi/
H A Ddc395x.h31 #define DC395x_SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40 MHz) */
343 /* 000 100ns, 10.0 MHz */
344 /* 001 150ns, 6.6 MHz */
345 /* 010 200ns, 5.0 MHz */
346 /* 011 250ns, 4.0 MHz */
347 /* 100 300ns, 3.3 MHz */
348 /* 101 350ns, 2.8 MHz */
349 /* 110 400ns, 2.5 MHz */
350 /* 111 450ns, 2.2 MHz */
355 /* 000 50ns, 20.0 MHz */
[all …]
/linux/arch/arm/mach-omap2/
H A Dopp2xxx.h123 /* 2420-PRCM III 532MHz core */
124 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
125 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
126 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
131 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
133 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
134 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
136 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
141 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
144 /* 2420-PRCM II 600MHz core */
[all …]
H A Dopp2430_data.c22 * XXX Missing 19.2MHz sys_clk rate sets.
56 {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
64 {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
72 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
80 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
88 {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
96 {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
104 {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
112 {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
120 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13MHz */
[all …]
/linux/Documentation/networking/dsa/
H A Dsja1105.rst16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
17 100base-TX PHYs
18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
19 - SJA1110C: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
20 - SJA1110D: Third generation, TTEthernet, SGMII, 100base-T1
135 ``swp5``. The traffic class gate for management traffic (7) is open for 100 us,
165 tc qdisc add dev swp5 parent root handle 100 taprio \
214 of 100 and a PCP of 0::
217 dst_mac 42:be:24:9b:76:20 vlan_id 100 vlan_prio 0 action drop
332 In the RMII spec, the 50 MHz clock signals are either driven by the MAC or by
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-myir-mys-6ulx.dtsi172 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
183 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
209 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
224 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
H A Dimx6sl-warp.dts168 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
184 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
211 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
222 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
/linux/tools/power/x86/turbostat/
H A Dturbostat.8156 \fBTSC_MHz\fP average MHz that the TSC ran during the entire interval.
190 …tage of time that CPUs are busy. If N CPUs are busy during an interval, the percentage is N * 100%.
210 …ary is the sum of the package throttling time, and thus may be higher than 100% on a multi-package…
214 \fBUncMHz\fP per-package uncore MHz, instantaneous sample.
216 \fBUMHz1.0\fP per-package uncore MHz for pm_domain=1 and fabric_cluster=0, instantaneous sample. S…
300 TSC: 3096 MHz (24000000 Hz * 258 / 2 / 1000000)
301 CPUID(0x16): base_mhz: 3100 max_mhz: 4200 bus_mhz: 100
305 8 * 100.0 = 800.0 MHz max efficiency frequency
306 31 * 100.0 = 3100.0 MHz base frequency
309 39 * 100.0 = 3900.0 MHz max turbo 4 active cores
[all …]
/linux/drivers/gpu/drm/gma500/
H A Doaktrail.h108 u8 Panel_Initial_Brightness;/* [7:0] 0 - 100% */
132 u16 MaxLaneFreq:3; /* 0: 100MHz, 1: 200MHz, 2: 300MHz, */
133 /*3: 400MHz, 4: 500MHz, 5: 600MHz, 6: 700MHz, 7: 800MHz.*/
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dintel,pinctrl-keembay.yaml78 0 - Fast(~100MHz)
79 1 - Slow(~50MHz)
112 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
/linux/drivers/phy/broadcom/
H A Dphy-bcm-ns2-pcie.c21 /* select the AFE 100MHz block page */ in ns2_pci_phy_init()
26 /* set the 100 MHz reference clock amplitude to 2.05 v */ in ns2_pci_phy_init()
/linux/Documentation/i2c/busses/
H A Di2c-ali15x3.rst52 100MHz CPU Front Side bus
53 * "Aladdin V" includes the M1541 Socket 7 North bridge with AGP and 100MHz
68 with host bus up to 83.3 MHz.
/linux/arch/x86/kvm/vmx/
H A Dtdx_arch.h127 * TDX requires the frequency to be defined in units of 25MHz, which is the
129 * module can only program frequencies that are multiples of 25MHz. The
130 * frequency must be between 100mhz and 10ghz (inclusive).
134 #define TDX_MIN_TSC_FREQUENCY_KHZ (100 * 1000)

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