Lines Matching +full:100 +full:mhz

16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
17   100base-TX PHYs
18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
19 - SJA1110C: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
20 - SJA1110D: Third generation, TTEthernet, SGMII, 100base-T1
135 ``swp5``. The traffic class gate for management traffic (7) is open for 100 us,
165   tc qdisc add dev swp5 parent root handle 100 taprio \
214 of 100 and a PCP of 0::
217           dst_mac 42:be:24:9b:76:20 vlan_id 100 vlan_prio 0 action drop
332 In the RMII spec, the 50 MHz clock signals are either driven by the MAC or by
336 the 50 MHz clock themselves, in an attempt to be helpful.
350 100Base-Tx wire.
370 In RGMII the clock frequency changes with link speed (125 MHz at 1000 Mbps, 25
371 MHz at 100 Mbps and 2.5 MHz at 10 Mbps), and link speed might change during the
382 Ethernet controllers out there which come out of reset in 100 Mbps mode, and
397 internal 100base-T1 PHYs can be accessed from the host. This is, however, not
398 used by the driver, instead the internal 100base-T1 and 100base-TX PHYs are
430 1      100base-TX     100base-TX     100base-TX
439 5      100base-T1     100base-T1     100base-T1     100base-T1
440 6      100base-T1     100base-T1     100base-T1     100base-T1
441 7      100base-T1     100base-T1     100base-T1     100base-T1
442 8      100base-T1     100base-T1     n/a            n/a
443 9      100base-T1     100base-T1     n/a            n/a
444 10     100base-T1     n/a            n/a            n/a