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/freebsd/lib/libpmc/pmu-events/arch/x86/ivytown/
H A Duncore-power.json10 …quency that is configured in the filter. (filter_band0=XXX, with XXX in 100Mhz units). One can al…
14 "MetricExpr": "(UNC_P_FREQ_BAND0_CYCLES / UNC_P_CLOCKTICKS) * 100.",
20 …quency that is configured in the filter. (filter_band1=XXX, with XXX in 100Mhz units). One can al…
24 "MetricExpr": "(UNC_P_FREQ_BAND1_CYCLES / UNC_P_CLOCKTICKS) * 100.",
30 …quency that is configured in the filter. (filter_band2=XXX, with XXX in 100Mhz units). One can al…
34 "MetricExpr": "(UNC_P_FREQ_BAND2_CYCLES / UNC_P_CLOCKTICKS) * 100.",
40 …quency that is configured in the filter. (filter_band3=XXX, with XXX in 100Mhz units). One can al…
44 "MetricExpr": "(UNC_P_FREQ_BAND3_CYCLES / UNC_P_CLOCKTICKS) * 100.",
50 …quency that is configured in the filter. (filter_band0=XXX, with XXX in 100Mhz units). One can al…
55 "MetricExpr": "(UNC_P_FREQ_BAND0_CYCLES / UNC_P_CLOCKTICKS) * 100.",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/jaketown/
H A Duncore-power.json10 …equency that is configured in the filter. (filter_band0=XXX with XXX in 100Mhz units). One can al…
14 "MetricExpr": "(UNC_P_FREQ_BAND0_CYCLES / UNC_P_CLOCKTICKS) * 100.",
20 …equency that is configured in the filter. (filter_band1=XXX with XXX in 100Mhz units). One can al…
24 "MetricExpr": "(UNC_P_FREQ_BAND1_CYCLES / UNC_P_CLOCKTICKS) * 100.",
30 …equency that is configured in the filter. (filter_band2=XXX with XXX in 100Mhz units). One can al…
34 "MetricExpr": "(UNC_P_FREQ_BAND2_CYCLES / UNC_P_CLOCKTICKS) * 100.",
40 …quency that is configured in the filter. (filter_band3=XXX, with XXX in 100Mhz units). One can al…
44 "MetricExpr": "(UNC_P_FREQ_BAND3_CYCLES / UNC_P_CLOCKTICKS) * 100.",
50 …equency that is configured in the filter. (filter_band0=XXX with XXX in 100Mhz units). One can al…
55 "MetricExpr": "(UNC_P_FREQ_BAND0_CYCLES / UNC_P_CLOCKTICKS) * 100.",
[all …]
/freebsd/sys/x86/cpufreq/
H A Dest.c84 /* Convert MHz and mV into IDs for passing to the MSR. */
85 #define ID16(MHz, mV, bus_clk) \ argument
86 (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4))
91 #define FREQ_INFO_PWR(MHz, mV, bus_clk, mW) \ argument
92 { MHz, mV, ID16(MHz, mV, bus_clk), mW }
93 #define FREQ_INFO(MHz, mV, bus_clk) \ argument
94 FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN)
106 #define INTEL_BUS_CLK 100
116 * Frequency (MHz) and voltage (mV) settings.
665 * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants.
[all …]
/freebsd/contrib/wpa/src/common/
H A Dieee802_11_common.c1375 * @freq: Frequency (MHz) to convert
1504 /* 5 GHz, channels 100..144 */ in ieee80211_freq_to_channel_ext()
1701 case 32: /* channels 1..7; 40 MHz */ in ieee80211_chan_to_freq_us()
1702 case 33: /* channels 5..11; 40 MHz */ in ieee80211_chan_to_freq_us()
1708 case 22: /* channels 36,44; 40 MHz */ in ieee80211_chan_to_freq_us()
1709 case 23: /* channels 52,60; 40 MHz */ in ieee80211_chan_to_freq_us()
1710 case 27: /* channels 40,48; 40 MHz */ in ieee80211_chan_to_freq_us()
1711 case 28: /* channels 56,64; 40 MHz */ in ieee80211_chan_to_freq_us()
1715 case 4: /* channels 100-144 */ in ieee80211_chan_to_freq_us()
1716 case 24: /* channels 100-140; 40 MHz */ in ieee80211_chan_to_freq_us()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/input/touchscreen/
H A Dstmpe.txt16 2 -> 100 us
24 1 -> 100 us
30 7 -> 100 ms
53 0 -> 1.625 MHz
54 1 -> 3.25 MHz
55 2 || 3 -> 6.5 MHz
78 /* 3.25 MHz ADC clock speed */
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Diss4xx-mpic.dts38 clock-frequency = <100000000>; // 100Mhz :-)
52 clock-frequency = <100000000>; // 100Mhz :-)
68 clock-frequency = <100000000>; // 100Mhz :-)
84 clock-frequency = <100000000>; // 100Mhz :-)
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dcpu-capacity.txt38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
105 entry-latency-us = <100>;
128 capacity-dmips-mhz = <1024>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/cpu/
H A Dcpu-capacity.txt38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
105 entry-latency-us = <100>;
128 capacity-dmips-mhz = <1024>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/ata/
H A Dqcom-sata.txt26 100Mhz (100000000) for SATA_RXOOB_CLK
27 100Mhz (100000000) for SATA_PMALIVE_CLK
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6sx-softing-vining-2000.dts116 max-speed = <100>;
139 max-speed = <100>;
417 pinctrl_usdhc2_50mhz: usdhc2grp-50mhz {
430 pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
441 pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
452 pinctrl_usdhc4_50mhz: usdhc4grp-50mhz {
468 pinctrl_usdhc4_100mhz: usdhc4-100mhz {
483 pinctrl_usdhc4_200mhz: usdhc4-200mhz {
H A Dimx6sl-tolino-shine3.dts193 pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
204 pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
237 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
248 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
H A Dimx6sll-kobo-clarahd.dts203 pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
214 pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
247 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
258 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Drs.h14 * bandwidths <= 80MHz
16 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
37 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
38 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
39 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
40 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
41 * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel
122 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
123 * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz
146 * <nss, channel-width> pair (0 - 80mhz widt
[all...]
H A Dlocation.h101 * @IWL_TOF_BW_20_LEGACY: 20 MHz non-HT
102 * @IWL_TOF_BW_20_HT: 20 MHz HT
103 * @IWL_TOF_BW_40: 40 MHz
104 * @IWL_TOF_BW_80: 80 MHz
105 * @IWL_TOF_BW_160: 160 MHz
510 * in units of 100us. 0 means no preference by station
511 * @ftm_format_and_bw20M: FTM Channel Spacing/Format for 20MHz: recommended
513 * @ftm_format_and_bw40M: FTM Channel Spacing/Format for 40MHz: recommended
515 * @ftm_format_and_bw80M: FTM Channel Spacing/Format for 80MHz: recommended
549 * periodicity In units of 100m
[all...]
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-exynos5.txt4 at various speeds ranging from 100khz to 3.4Mhz.
31 at 100khz.
33 clock-frequency is >= 1Mhz.
H A Di2c-exynos5.yaml14 at various speeds ranging from 100kHz to 3.4MHz.
52 If not specified, the bus operates in fast-speed mode at 100kHz.
55 clock-frequency is >= 1MHz.
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dmicrel.txt23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
48 100base-fx (full and half duplex) modes.
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-g12b.dtsi51 capacity-dmips-mhz = <592>;
61 capacity-dmips-mhz = <592>;
66 cpu100: cpu@100 {
71 capacity-dmips-mhz = <1024>;
81 capacity-dmips-mhz = <1024>;
91 capacity-dmips-mhz = <1024>;
101 capacity-dmips-mhz = <1024>;
H A Dmeson-gxm.dtsi46 capacity-dmips-mhz = <1024>;
50 capacity-dmips-mhz = <1024>;
54 capacity-dmips-mhz = <1024>;
58 capacity-dmips-mhz = <1024>;
61 cpu4: cpu@100 {
66 capacity-dmips-mhz = <1024>;
77 capacity-dmips-mhz = <1024>;
88 capacity-dmips-mhz = <1024>;
99 capacity-dmips-mhz = <1024>;
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dintel,pinctrl-keembay.yaml78 0 - Fast(~100MHz)
79 1 - Slow(~50MHz)
112 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
/freebsd/sys/arm/freescale/imx/
H A Dimx6_anatop.c119 * 396MHz, it also says that the ARM and SOC voltages can't differ by
124 uint32_t mhz; member
136 * value (0-3) from the ocotp CFG3 register into a mhz value that can be looked
266 d = abs((int)cpu_newmhz - (int)imx6_oppt_table[i].mhz); in cpufreq_nearest_oppt()
281 if (op->mhz > sc->cpu_curmhz) { in cpufreq_set_clock()
289 * - Set the PLL into bypass mode; cpu should now be running at 24mhz. in cpufreq_set_clock()
294 cpufreq_mhz_to_div(sc, op->mhz, &corediv, &plldiv); in cpufreq_set_clock()
316 if (op->mhz < sc->cpu_curmhz) in cpufreq_set_clock()
318 sc->cpu_curmhz = op->mhz; in cpufreq_set_clock()
341 if (op->mhz > sc->cpu_maxmhz) in cpufreq_sysctl_minmhz()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5422-cpus.dtsi56 cpu0: cpu@100 {
65 capacity-dmips-mhz = <539>;
78 capacity-dmips-mhz = <539>;
91 capacity-dmips-mhz = <539>;
104 capacity-dmips-mhz = <539>;
117 capacity-dmips-mhz = <1024>;
130 capacity-dmips-mhz = <1024>;
143 capacity-dmips-mhz = <1024>;
156 capacity-dmips-mhz = <1024>;
H A Dexynos5420-cpus.dtsi66 capacity-dmips-mhz = <1024>;
78 capacity-dmips-mhz = <1024>;
90 capacity-dmips-mhz = <1024>;
102 capacity-dmips-mhz = <1024>;
105 cpu4: cpu@100 {
114 capacity-dmips-mhz = <539>;
126 capacity-dmips-mhz = <539>;
138 capacity-dmips-mhz = <539>;
150 capacity-dmips-mhz = <539>;
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c131 PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz)
132 PLLU: Clock source for USB PHY, provides 12/60/480 MHz
136 PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum)
216 /* PLLM: 880 MHz Clock source for EMC 2x clock */
240 /* PLLC: 600 MHz Clock source for general use */
253 /* PLLC2: 600 MHz Clock source for engine scaling */
264 /* PLLC3: 600 MHz Clock source for engine scaling */
275 /* PLLC4: 600 MHz Clock source for ISP/VI units */
288 /* PLLP: 408 MHz Clock source for most peripherals */
298 /* PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz) */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-rockchip-naneng-combphy.yaml59 By default the internal clock is selected. The PCIe PHY provides a 100MHz
61 When selecting this option an externally 100MHz differential

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