Lines Matching +full:100 +full:mhz
131 PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz)
132 PLLU: Clock source for USB PHY, provides 12/60/480 MHz
136 PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum)
216 /* PLLM: 880 MHz Clock source for EMC 2x clock */
240 /* PLLC: 600 MHz Clock source for general use */
253 /* PLLC2: 600 MHz Clock source for engine scaling */
264 /* PLLC3: 600 MHz Clock source for engine scaling */
275 /* PLLC4: 600 MHz Clock source for ISP/VI units */
288 /* PLLP: 408 MHz Clock source for most peripherals */
298 /* PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz) */
308 /* PLLU: 480 MHz Clock source for USB PHY, provides 12/60/480 MHz */
319 /* PLLD: 600 MHz Clock sources for the DSI and display subsystem */
329 /* PLLD2: 600 MHz Clock sources for the DSI and display subsystem */
355 /* PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum) */
365 /* PLLDP: 600 MHz Clock source for eDP/LVDS (spread spectrum) */
797 #define PLLD2_PFD_MIN 12000000 /* 12 MHz */
798 #define PLLD2_PFD_MAX 38000000 /* 38 MHz */
799 #define PLLD2_VCO_MIN 600000000 /* 600 MHz */
861 if (best_err > ((*fout * 100) / 4)) in plld2_set_freq()
926 DELAY(100); in pllx_set_freq()
983 if (*fout == 480000000) /* PLLU is fixed to 480 MHz */ in tegra124_pll_set_freq()
1083 * XXX Simplified UTMIP settings for 12MHz base clock. in config_utmi_pll()