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/linux/include/uapi/linux/
H A Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * linux/mii.h: definitions for MII-compatible transceivers
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
30 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
42 #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
55 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
58 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
60 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
63 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb/
H A Dmv88e1xxx.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 #define MII_GBCR 9 /* 1000Base-T control register */
19 #define MII_GBSR 10 /* 1000Base-T status register */
21 /* 1000Base-T control register fields */
28 /* 1000Base-T status register fields */
72 #define V_PSCR_MDI_XOVER_MODE(x) ((x) << S_PSCR_MDI_XOVER_MODE) argument
73 #define G_PSCR_MDI_XOVER_MODE(x) (((x) >> S_PSCR_MDI_XOVER_MODE) & M_PSCR_MDI_XOVER_MODE) argument
81 #define V_DOWNSHIFT_CNT(x) ((x) << S_DOWNSHIFT_CNT) argument
82 #define G_DOWNSHIFT_CNT(x) (((x) >> S_DOWNSHIFT_CNT) & M_DOWNSHIFT_CNT) argument
108 #define V_PSSR_CABLE_LEN(x) ((x) << S_PSSR_CABLE_LEN) argument
[all …]
/linux/drivers/net/ethernet/ti/
H A Dnetcp_sgmii.c1 // SPDX-License-Identifier: GPL-2.0
7 * Sandeep Paulraj <s-paulraj@ti.com>
8 * Wingman Kwok <w-kwok2@ti.com>
22 #define SGMII23_OFFSET(x) ((x - 2) * 0x100) argument
23 #define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : (SGMII23_OFFSET(x))) argument
26 #define SGMII_SRESET_REG(x) (SGMII_OFFSET(x) + 0x004) argument
27 #define SGMII_CTL_REG(x) (SGMII_OFFSET(x) + 0x010) argument
28 #define SGMII_STATUS_REG(x) (SGMII_OFFSET(x) + 0x014) argument
29 #define SGMII_MRADV_REG(x) (SGMII_OFFSET(x) + 0x018) argument
31 static void sgmii_write_reg(void __iomem *base, int reg, u32 val) in sgmii_write_reg() argument
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
H A Dqcom,qca807x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Marangi <ansuelsmth@gmail.com>
11 - Robert Marko <robert.marko@sartura.hr>
15 IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and
16 1000BASE-T PHY-s.
21 Both models have a combo port that supports 1000BASE-X and
22 100BASE-FX fiber.
25 output only pins that natively drive LED-s for up to 2 attached
[all …]
H A Dmicrochip,lan966x-switch.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
14 two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
16 2 Quad-SGMII/Quad-USGMII interfaces.
20 pattern: "^switch@[0-9a-f]+$"
[all …]
/linux/arch/arm/boot/dts/nxp/vf/
H A Dvf610-zii-scu4-aib.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 // Copyright (C) 2016-2018 Zodiac Inflight Innovations
5 /dts-v1/;
10 compatible = "zii,vf610scu4-aib", "zii,vf610dev", "fsl,vf610";
13 stdout-path = &uart0;
21 gpio-leds {
22 compatible = "gpio-leds";
23 pinctrl-0 = <&pinctrl_leds_debug>;
24 pinctrl-names = "default";
26 led-debug {
[all …]
/linux/drivers/net/ethernet/atheros/atlx/
H A Datlx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* atlx_hw.h -- common hardware definitions for Attansic network drivers
4 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
5 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
6 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
10 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
26 #define SPEED_1000 1000
149 /* IRQ Anti-Lost Timer Initial Value Register */
228 /* MAC Half-Duplex Control Register */
246 /* Wake-On-Lan control register */
[all …]
/linux/drivers/pwm/
H A Dpwm-hibvt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
18 #define PWM_CFG0_ADDR(x) (((x) * 0x20) + 0x0) argument
19 #define PWM_CFG1_ADDR(x) (((x) * 0x20) + 0x4) argument
20 #define PWM_CFG2_ADDR(x) (((x) * 0x20) + 0x8) argument
21 #define PWM_CTRL_ADDR(x) (((x) * 0x20) + 0xC) argument
37 void __iomem *base; member
70 static void hibvt_pwm_set_bits(void __iomem *base, u32 offset, in hibvt_pwm_set_bits() argument
73 void __iomem *address = base + offset; in hibvt_pwm_set_bits()
86 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_enable()
94 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_disable()
[all …]
/linux/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_crtc.c1 // SPDX-License-Identifier: GPL-2.0
30 for_each_new_connector_in_state(crtc_st->state, conn, conn_st, i) { in komeda_crtc_get_color_config()
31 if (conn_st->crtc != crtc_st->crtc) in komeda_crtc_get_color_config()
34 conn_bpc = conn->display_info.bpc ? conn->display_info.bpc : 8; in komeda_crtc_get_color_config()
35 conn_color_formats &= conn->display_info.color_formats; in komeda_crtc_get_color_config()
53 if (!kcrtc_st->base.active) { in komeda_crtc_update_clock_ratio()
54 kcrtc_st->clock_ratio = 0; in komeda_crtc_update_clock_ratio()
58 pxlclk = kcrtc_st->base.adjusted_mode.crtc_clock * 1000ULL; in komeda_crtc_update_clock_ratio()
61 kcrtc_st->clock_ratio = div64_u64(aclk << 32, pxlclk); in komeda_crtc_update_clock_ratio()
65 * komeda_crtc_atomic_check - build display output data flow
[all …]
/linux/drivers/scsi/pcmcia/
H A Dnsp_cs.c3 NinjaSCSI-3 / NinjaSCSI-32Bi PCMCIA SCSI host adapter card driver
21 I-O DATA PCSC-F (Workbit NinjaSCSI-3)
22 "WBT", "NinjaSCSI-3", "R1.0"
23 I-O DATA CBSC-II (Workbit NinjaSCSI-32Bi in 16bit mode)
56 MODULE_DESCRIPTION("WorkBit NinjaSCSI-3 / NinjaSCSI-32Bi(16bit) PCMCIA SCSI host adapter module");
81 .name = "WorkBit NinjaSCSI-3/32Bi(16bit)",
90 .dma_boundary = PAGE_SIZE - 1,
94 static nsp_hw_data nsp_data_base; /* attach <-> detect glue */
169 printk("nsp_cs-debug: 0x%x %s (%d): %s\n", mask, func, line, buf); in nsp_cs_dmessage()
178 * You must be set SCpnt->result before call this function.
[all …]
/linux/drivers/gpu/drm/radeon/
H A Drs690.c42 for (i = 0; i < rdev->usec_timeout; i++) { in rs690_mc_wait_for_idle()
49 return -1; in rs690_mc_wait_for_idle()
74 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, in rs690_pm_info()
76 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset); in rs690_pm_info()
82 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock)); in rs690_pm_info()
83 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); in rs690_pm_info()
84 if (le16_to_cpu(info->info.usK8MemoryClock)) in rs690_pm_info()
85 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); in rs690_pm_info()
86 else if (rdev->clock.default_mclk) { in rs690_pm_info()
87 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); in rs690_pm_info()
[all …]
/linux/Documentation/admin-guide/pm/
H A Dintel-speed-select.rst1 .. SPDX-License-Identifier: GPL-2.0
14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
19 dynamically without pre-configuring via BIOS setup options. This dynamic
29 intel-speed-select configuration tool
32 Most Linux distribution packages may include the "intel-speed-select" tool. If not,
38 # cd tools/power/x86/intel-speed-select/
43 ------------
47 # intel-speed-select --help
49 The top-level help describes arguments and features. Notice that there is a
[all …]
/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-sgmii.c7 * Copyright (C) 2003-2018 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
35 #include <asm/octeon/cvmx-config.h>
37 #include <asm/octeon/cvmx-helper.h>
38 #include <asm/octeon/cvmx-helper-board.h>
40 #include <asm/octeon/cvmx-gmxx-defs.h>
41 #include <asm/octeon/cvmx-pcsx-defs.h>
42 #include <asm/octeon/cvmx-pcsxx-defs.h>
54 const uint64_t clock_mhz = cvmx_sysinfo_get()->cpu_clock_hz / 1000000; in __cvmx_helper_sgmii_hardware_init_one_time()
[all …]
/linux/drivers/net/ethernet/oki-semi/pch_gbe/
H A Dpch_gbe_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1999 - 2010 Intel Corporation.
12 #define PHY_MAX_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
14 /* PHY 1000 MII Register/Bit Definitions */
21 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
25 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Register */
26 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Register */
34 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
41 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
61 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
[all …]
/linux/drivers/regulator/
H A Dtwl-regulator.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * twl-regulator.c -- support regulators in twl4030/twl6030 family chips
25 * These chips are often used in OMAP-based systems.
27 * This driver implements software-based resource control for various
34 u8 base; member
39 /* voltage in mV = table[VSEL]; table_len must be a power-of-two */
57 /* LDO control registers ... offset is from the base of its register bank.
81 &value, info->base + offset); in twlreg_read()
90 value, info->base + offset); in twlreg_write()
93 /*----------------------------------------------------------------------*/
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dmcp77.c24 #define mcp77_clk(p) container_of((p), struct mcp77_clk, base)
33 struct nvkm_clk base; member
44 struct nvkm_device *device = clk->base.subdev.device; in read_div()
49 read_pll(struct mcp77_clk *clk, u32 base) in read_pll() argument
51 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
52 u32 ctrl = nvkm_rd32(device, base + 0); in read_pll()
53 u32 coef = nvkm_rd32(device, base + 4); in read_pll()
54 u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll()
59 switch (base){ in read_pll()
81 mcp77_clk_read(struct nvkm_clk *base, enum nv_clk_src src) in mcp77_clk_read() argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.c48 CTX->logger
89 if (delay_us >= 1000) in dcn301_smu_wait_for_response()
90 msleep(delay_us/1000); in dcn301_smu_wait_for_response()
93 } while (max_retries--); in dcn301_smu_wait_for_response()
110 return -1; in dcn301_smu_send_msg_with_param()
139 DC_LOG_DEBUG("%s %x\n", __func__, smu_version); in dcn301_smu_get_smu_version()
147 int actual_dispclk_set_mhz = -1; in dcn301_smu_set_dispclk()
157 return actual_dispclk_set_mhz * 1000; in dcn301_smu_set_dispclk()
162 int actual_dprefclk_set_mhz = -1; in dcn301_smu_set_dprefclk()
164 DC_LOG_DEBUG("%s %d\n", __func__, clk_mgr->base.dprefclk_khz / 1000); in dcn301_smu_set_dprefclk()
[all …]
/linux/drivers/i2c/busses/
H A Di2c-owl.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: David Liu <liuwei@actions-semi.com>
37 #define OWL_I2C_CTL_GBCC(x) (((x) & 0x3) << 2) argument
47 #define OWL_I2C_DIV_FACTOR(x) ((x) & 0xff) argument
72 #define OWL_I2C_CMD_AS(x) (((x) & 0x7) << 1) argument
73 #define OWL_I2C_CMD_SAS(x) (((x) & 0x7) << 5) argument
89 #define OWL_I2C_TIMEOUT_MS (4 * 1000)
100 void __iomem *base; member
123 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, in owl_i2c_reset()
126 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, in owl_i2c_reset()
[all …]
/linux/include/linux/
H A Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/mii.h: definitions for MII-compatible transceivers
53 return (struct mii_ioctl_data *) &rq->ifr_ifru; in if_mii()
66 * between 100T-full and 100T-half. If your phy does not support
90 * @duplex_lock: Non-zero if duplex is locked at full
196 * MII_CTRL1000 register when in 1000T mode.
216 * MII_CTRL1000 register when in 1000T mode.
238 * bits, when in 1000Base-T mode, to ethtool
258 * bits, when in 1000Base-T mode, to ethtool
276 * bits, when in 1000Base-T mode, to ethtool
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramgt215.c25 #define gt215_ram(p) container_of((p), struct gt215_ram, base)
39 struct ramfuc base; member
94 struct nvkm_ram base; member
120 hi--; in gt215_link_train_calc()
125 median[i] = ((hi - lo) >> 1) + lo; in gt215_link_train_calc()
138 train->r_100720 = 0; in gt215_link_train_calc()
143 train->r_100720 |= ((median[i] & 0x0f) << (i << 2)); in gt215_link_train_calc()
146 train->r_1111e0 = 0x02000000 | (bin * 0x101); in gt215_link_train_calc()
147 train->r_111400 = 0x0; in gt215_link_train_calc()
156 struct gt215_ltrain *train = &ram->ltrain; in gt215_link_train()
[all …]
/linux/arch/mips/alchemy/common/
H A Dusb.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * area. Au1550 has OHCI on different base address. No need to handle
20 #include <asm/mach-au1x00/au1000.h>
28 #define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */
32 #define USBHEN_BE (1 << 0) /* OHCI Big-Endian */
43 #define USBCFG_FLA(x) (((x) & 0x3f) << 8) argument
98 static inline void __au1300_usb_phyctl(void __iomem *base, int enable) in __au1300_usb_phyctl() argument
102 r = __raw_readl(base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
103 s = __raw_readl(base + USB_DWC_CTRL3); in __au1300_usb_phyctl()
112 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
[all …]
/linux/drivers/net/phy/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
40 Adds support for a set of LED trigger events per-PHY. Link
44 logical-or of all the link speed ones.
69 Currently tested with mpc866ads and mpc8349e-mitx.
121 - ADIN1200 - Robust,Industrial, Low Power 10/100 Ethernet PHY
122 - ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
130 - ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY
144 Currently supports the Asix Electronics PHY found in the X-Surf 100
153 found in the X-Surf 100 AX88796B package.
270 Support for the Marvell 88Q2XXX 100/1000BASE-T1 Automotive Ethernet
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-388-clearfog.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include "armada-388-clearfog.dtsi"
13 compatible = "solidrun,clearfog-pro-a1", "solidrun,clearfog-a1",
18 internal-regs {
28 reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
34 gpio-keys {
35 compatible = "gpio-keys";
36 pinctrl-0 = <&rear_button_pins>;
37 pinctrl-names = "default";
[all …]
/linux/drivers/memory/
H A Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
33 #include <linux/omap-gpmc.h>
37 #include <linux/platform_data/mtd-nand-omap2.h>
39 #define DEVICE_NAME "omap-gpmc"
258 /* Define chip-selects as reserved by default until probe completes */
299 rate /= 1000; in gpmc_get_fclk_period()
306 * gpmc_get_clk_period - get period of selected clock domain in ps
343 return (time_ns * 1000 + tick_ps - 1) / tick_ps; in gpmc_ns_to_clk_ticks()
[all …]

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