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/linux/drivers/net/phy/
H A Dsmsc.c30 #define PHY_EDPD_CONFIG_EXT_CROSSOVER_ 0x0001
34 #define SPECIAL_CTRL_STS_OVRRD_AMDIX_ 0x8000
35 #define SPECIAL_CTRL_STS_AMDIX_ENABLE_ 0x4000
36 #define SPECIAL_CTRL_STS_AMDIX_STATE_ 0x2000
63 return rc < 0 ? rc : 0; in smsc_phy_ack_interrupt()
78 rc = phy_write(phydev, MII_LAN83C185_IM, 0); in smsc_phy_config_intr()
85 return rc < 0 ? rc : 0; in smsc_phy_config_intr()
106 if (irq_status < 0) { in smsc_phy_handle_interrupt()
127 return 0; in smsc_phy_config_init()
140 if (rc < 0) in smsc_phy_reset()
[all …]
H A Ddp83822.c17 #define DP83822_PHY_ID 0x2000a240
18 #define DP83825S_PHY_ID 0x2000a140
19 #define DP83825I_PHY_ID 0x2000a150
20 #define DP83825CM_PHY_ID 0x2000a160
21 #define DP83825CS_PHY_ID 0x2000a170
22 #define DP83826C_PHY_ID 0x2000a130
23 #define DP83826NC_PHY_ID 0x2000a110
25 #define MII_DP83822_CTRL_2 0x0a
26 #define MII_DP83822_PHYSTS 0x10
27 #define MII_DP83822_PHYSCR 0x11
[all …]
/linux/drivers/net/
H A Dsungem_phy.c37 { 0, 0, 0 }, /* No link */
38 { 0, 0, 0 }, /* 10BT Half Duplex */
39 { 1, 0, 0 }, /* 10BT Full Duplex */
40 { 0, 1, 0 }, /* 100BT Half Duplex */
41 { 0, 1, 0 }, /* 100BT Half Duplex */
42 { 1, 1, 0 }, /* 100BT Full Duplex*/
43 { 1, 0, 1 }, /* 1000BT */
44 { 1, 0, 1 }, /* 1000BT */
81 if ((val & BMCR_RESET) == 0) in reset_one_mii_phy()
85 if ((val & BMCR_ISOLATE) && limit > 0) in reset_one_mii_phy()
[all …]
/linux/include/uapi/linux/netfilter_bridge/
H A Debt_mark_t.h10 * action 0xfffffff0, the result will look ok for older
12 #define MARK_SET_VALUE (0xfffffff0)
13 #define MARK_OR_VALUE (0xffffffe0)
14 #define MARK_AND_VALUE (0xffffffd0)
15 #define MARK_XOR_VALUE (0xffffffc0)
/linux/arch/mips/loongson2ef/common/cs5536/
H A Dcs5536_ide.c17 u32 hi = 0, lo = value; in pci_ide_write_reg()
23 lo |= (0x03 << 4); in pci_ide_write_reg()
25 lo &= ~(0x03 << 4); in pci_ide_write_reg()
32 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; in pci_ide_write_reg()
38 value &= 0x0000ff00; in pci_ide_write_reg()
40 hi &= 0xffffff00; in pci_ide_write_reg()
49 } else if (value & 0x01) { in pci_ide_write_reg()
51 lo = (value & 0xfffffff0) | 0x1; in pci_ide_write_reg()
54 value &= 0xfffffffc; in pci_ide_write_reg()
55 hi = 0x60000000 | ((value & 0x000ff000) >> 12); in pci_ide_write_reg()
[all …]
/linux/net/netfilter/ipset/
H A Dpfxlen.c12 E(0x00000000, 0x00000000, 0x00000000, 0x00000000), \
13 E(0x80000000, 0x00000000, 0x00000000, 0x00000000), \
14 E(0xC0000000, 0x00000000, 0x00000000, 0x00000000), \
15 E(0xE0000000, 0x00000000, 0x00000000, 0x00000000), \
16 E(0xF0000000, 0x00000000, 0x00000000, 0x00000000), \
17 E(0xF8000000, 0x00000000, 0x00000000, 0x00000000), \
18 E(0xFC000000, 0x00000000, 0x00000000, 0x00000000), \
19 E(0xFE000000, 0x00000000, 0x00000000, 0x00000000), \
20 E(0xFF000000, 0x00000000, 0x00000000, 0x00000000), \
21 E(0xFF800000, 0x00000000, 0x00000000, 0x00000000), \
[all …]
/linux/drivers/atm/
H A Dnicstarmac.c30 #define CS_HIGH 0x0002 /* Chip select high */
31 #define CS_LOW 0x0000 /* Chip select low (active low) */
32 #define CLK_HIGH 0x0004 /* Clock high */
33 #define CLK_LOW 0x0000 /* Clock low */
34 #define SI_HIGH 0x0001 /* Serial input data high */
35 #define SI_LOW 0x0000 /* Serial input data low */
38 #if 0
42 CLK_HIGH, /* 0 */
44 CLK_HIGH, /* 0 */
46 CLK_HIGH, /* 0 */
[all …]
/linux/include/linux/soc/ixp4xx/
H A Dcpu.h17 /* Processor id value in CP15 Register 0 */
18 #define IXP42X_PROCESSOR_ID_VALUE 0x690541c0 /* including unused 0x690541Ex */
19 #define IXP42X_PROCESSOR_ID_MASK 0xffffffc0
21 #define IXP43X_PROCESSOR_ID_VALUE 0x69054040
22 #define IXP43X_PROCESSOR_ID_MASK 0xfffffff0
24 #define IXP46X_PROCESSOR_ID_VALUE 0x69054200 /* including IXP455 */
25 #define IXP46X_PROCESSOR_ID_MASK 0xfffffff0
28 #define IXP4XX_EXP_CNFG2 0x2c
32 #define IXP4XX_FEATURE_RCOMP (1 << 0)
85 #define cpu_is_ixp42x_rev_a0() ((read_cpuid_id() & (IXP42X_PROCESSOR_ID_MASK | 0xF)) == \
[all …]
/linux/arch/arm/mm/
H A Dproc-xscale.S60 * Reminder: the vector table is located at 0xffff0000-0xffff0fff.
62 #define CLEAN_ADDR 0xfffe0000
70 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
76 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
92 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
94 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
117 mrc p15, 0, r1, c1, c0, 1
119 mcr p15, 0, r1, c1, c0, 1
[all …]
H A Dproc-sa1100.S41 mov r0, #0
42 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
43 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
55 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
56 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
57 bic r0, r0, #0x1000 @ ...i............
58 bic r0, r0, #0x000e @ ............wca.
59 mcr p15, 0, r0, c1, c0, 0 @ disable caches
75 mov ip, #0
76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
[all …]
H A Dproc-feroceon.S48 mrc p15, 0, r0, c0, c0, 1 @ read cache type register
54 and r0, r0, #0xf
55 moveq r3, #0 @ 1-way
73 mov r0, #0
74 mcr p15, 1, r0, c15, c9, 0 @ clean L2
75 mcr p15, 0, r0, c7, c10, 4 @ drain WB
78 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
79 bic r0, r0, #0x1000 @ ...i............
80 bic r0, r0, #0x000e @ ............wca.
81 mcr p15, 0, r0, c1, c0, 0 @ disable caches
[all …]
/linux/drivers/net/phy/mscc/
H A Dmscc_main.c105 {MSCC_VDDMAC_3300, { 0, 2, 4, 7, 10, 17, 29, 53} },
106 {MSCC_VDDMAC_2500, { 0, 3, 6, 10, 14, 23, 37, 63} },
107 {MSCC_VDDMAC_1800, { 0, 5, 9, 16, 23, 35, 52, 76} },
108 {MSCC_VDDMAC_1500, { 0, 6, 14, 21, 29, 42, 58, 77} },
130 return 0; in vsc85xx_get_sset_count()
143 for (i = 0; i < priv->nstats; i++) in vsc85xx_get_strings()
154 if (val < 0) in vsc85xx_get_stat()
172 for (i = 0; i < priv->nstats; i++) in vsc85xx_get_stats()
203 return 0; in vsc85xx_mdix_get()
225 reg_val = 0; in vsc85xx_mdix_set()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/
H A Dg98.fuc0s23 ctx_dma_query: .b32 0
24 ctx_dma_src: .b32 0
25 ctx_dma_dst: .b32 0
27 ctx_query_address_high: .b32 0
28 ctx_query_address_low: .b32 0
29 ctx_query_counter: .b32 0
30 ctx_cond_address_high: .b32 0
31 ctx_cond_address_low: .b32 0
32 ctx_cond_off: .b32 0
33 ctx_src_address_high: .b32 0
[all …]
/linux/arch/sh/drivers/pci/
H A Dpci-sh7751.h13 #define SH7751_VENDOR_ID 0x1054
14 #define SH7751_DEVICE_ID 0x3505
15 #define SH7751R_DEVICE_ID 0x350e
18 #define SH7751_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
19 #define SH7751_PCI_CONFIG_SIZE 0x1000000 /* Config space size */
20 #define SH7751_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
21 #define SH7751_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
22 #define SH7751_PCI_IO_BASE 0xFE240000 /* IO space base address */
23 #define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */
25 #define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */
[all …]
/linux/arch/sh/include/cpu-sh3/cpu/
H A Dmmu_context.h10 #define MMU_PTEH 0xFFFFFFF0 /* Page table entry register HIGH */
11 #define MMU_PTEL 0xFFFFFFF4 /* Page table entry register LOW */
12 #define MMU_TTB 0xFFFFFFF8 /* Translation table base register */
13 #define MMU_TEA 0xFFFFFFFC /* TLB Exception Address */
15 #define MMUCR 0xFFFFFFE0 /* MMU Control Register */
18 #define MMU_TLB_ADDRESS_ARRAY 0xF2000000
19 #define MMU_PAGE_ASSOC_BIT 0x80
23 #define MMU_CONTROL_INIT 0x007 /* SV=0, TF=1, IX=1, AT=1 */
25 #define TRA 0xffffffd0
26 #define EXPEVT 0xffffffd4
[all …]
/linux/include/linux/
H A Dmarvell_phy.h6 #define MARVELL_PHY_ID_MASK 0xfffffff0
9 #define MARVELL_PHY_ID_88E1101 0x01410c60
10 #define MARVELL_PHY_ID_88E3082 0x01410c80
11 #define MARVELL_PHY_ID_88E1112 0x01410c90
12 #define MARVELL_PHY_ID_88E1111 0x01410cc0
13 #define MARVELL_PHY_ID_88E1118 0x01410e10
14 #define MARVELL_PHY_ID_88E1121R 0x01410cb0
15 #define MARVELL_PHY_ID_88E1145 0x01410cd0
16 #define MARVELL_PHY_ID_88E1149R 0x01410e50
17 #define MARVELL_PHY_ID_88E1240 0x01410e30
[all …]
/linux/drivers/gpu/drm/radeon/
H A Drv200d.h31 #define R_00015C_AGP_BASE_2 0x00015C
32 #define S_00015C_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0)
33 #define G_00015C_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF)
34 #define C_00015C_AGP_BASE_ADDR_2 0xFFFFFFF0
/linux/arch/powerpc/kernel/
H A Dcpu_specs_book3s_32.h12 .pvr_mask = 0xffff0000,
13 .pvr_value = 0x00030000,
17 .mmu_features = 0,
25 .pvr_mask = 0xffff0000,
26 .pvr_value = 0x00060000,
30 .mmu_features = 0,
38 .pvr_mask = 0xffff0000,
39 .pvr_value = 0x00070000,
43 .mmu_features = 0,
51 .pvr_mask = 0x7fff0000,
[all …]
/linux/arch/arm/mach-shmobile/
H A Dsetup-r8a7779.c18 #define HPBREG_BASE 0xfe700000
21 #define INT2SMSKCR0 0x822a0 /* Interrupt Submask Clear Register 0 */
22 #define INT2SMSKCR1 0x822a4 /* Interrupt Submask Clear Register 1 */
23 #define INT2SMSKCR2 0x822a8 /* Interrupt Submask Clear Register 2 */
24 #define INT2SMSKCR3 0x822ac /* Interrupt Submask Clear Register 3 */
25 #define INT2SMSKCR4 0x822b0 /* Interrupt Submask Clear Register 4 */
27 #define INT2NTSR0 0x00060 /* Interrupt Notification Select Register 0 */
28 #define INT2NTSR1 0x00064 /* Interrupt Notification Select Register 1 */
32 void __iomem *base = ioremap(HPBREG_BASE, 0x00100000); in r8a7779_init_irq_dt()
37 writel(0xffffffff, base + INT2NTSR0); in r8a7779_init_irq_dt()
[all …]
/linux/arch/arm/include/asm/hardware/
H A Dcache-aurora-l2.h14 #define AURORA_SYNC_REG 0x700
15 #define AURORA_RANGE_BASE_ADDR_REG 0x720
16 #define AURORA_FLUSH_PHY_ADDR_REG 0x7f0
17 #define AURORA_INVAL_RANGE_REG 0x774
18 #define AURORA_CLEAN_RANGE_REG 0x7b4
19 #define AURORA_FLUSH_RANGE_REG 0x7f4
23 (0x3 << AURORA_ACR_REPLACEMENT_OFFSET)
25 (0 << AURORA_ACR_REPLACEMENT_OFFSET)
34 #define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET 0
36 (0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
[all …]
/linux/drivers/pci/hotplug/
H A Dcpqphp_pci.c47 int status = 0; in detect_HRT_floating_pointer()
81 func->pci_dev = pci_get_domain_bus_and_slot(0, func->bus, in cpqhp_configure_device()
93 func->pci_dev = pci_get_domain_bus_and_slot(0, func->bus, in cpqhp_configure_device()
113 return 0; in cpqhp_configure_device()
124 for (j = 0; j < 8 ; j++) { in cpqhp_unconfigure_device()
125 struct pci_dev *temp = pci_get_domain_bus_and_slot(0, in cpqhp_unconfigure_device()
135 return 0; in cpqhp_unconfigure_device()
147 int rc = 0; in cpqhp_set_irq()
175 temp_word = inb(0x4d0); in cpqhp_set_irq()
176 temp_word |= inb(0x4d1) << 8; in cpqhp_set_irq()
[all …]
/linux/drivers/char/agp/
H A Dali-agp.c13 #define ALI_AGPCTRL 0xb8
14 #define ALI_ATTBASE 0xbc
15 #define ALI_TLBCTRL 0xc0
16 #define ALI_TAGCTRL 0xc4
17 #define ALI_CACHE_FLUSH_CTRL 0xD0
18 #define ALI_CACHE_FLUSH_ADDR_MASK 0xFFFFF000
19 #define ALI_CACHE_FLUSH_EN 0x100
28 temp &= ~(0xfffffff0); in ali_fetch_size()
31 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { in ali_fetch_size()
40 return 0; in ali_fetch_size()
[all …]
/linux/arch/hexagon/include/asm/
H A Dvm_mmu.h24 #define __HVM_PDE_S (0x7 << 0)
25 #define __HVM_PDE_S_4KB 0
35 #define __HVM_PDE_PTMASK_4KB 0xfffff000
36 #define __HVM_PDE_PTMASK_16KB 0xfffffc00
37 #define __HVM_PDE_PTMASK_64KB 0xffffff00
38 #define __HVM_PDE_PTMASK_256KB 0xffffffc0
39 #define __HVM_PDE_PTMASK_1MB 0xfffffff0
46 #define __HVM_PTE_C (0x7<<6)
56 #define __HEXAGON_C_WB 0x0 /* Write-back, no L2 */
57 #define __HEXAGON_C_WT 0x1 /* Write-through, no L2 */
[all …]
/linux/arch/sh/include/asm/
H A Dentry-macros.S6 or #0xf0, r0
11 mov #0xfffffff0, r11
27 mov #((THREAD_SIZE - 1) >> 10) ^ 0xff, \tmp
/linux/drivers/char/tpm/
H A Dtpm_ppi.c33 GUID_INIT(0x3DDDFAA6, 0x361B, 0x4EB4,
34 0xA4, 0x24, 0x8D, 0x10, 0x08, 0x9D, 0x16, 0x53);
81 if (strcmp(chip->ppi_version, "1.2") < 0) in tpm_show_ppi_request()
91 * The first is function return code, 0 means success and 1 means in tpm_show_ppi_request()
92 * error. The second is pending TPM operation requested by the OS, 0 in tpm_show_ppi_request()
93 * means none and >0 means operation value. in tpm_show_ppi_request()
96 obj->package.elements[0].type == ACPI_TYPE_INTEGER && in tpm_show_ppi_request()
99 if (obj->package.elements[0].integer.value) in tpm_show_ppi_request()
110 obj->package.elements[0].type == ACPI_TYPE_INTEGER && in tpm_show_ppi_request()
112 if (obj->package.elements[0].integer.value) in tpm_show_ppi_request()
[all …]

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