1*0fdebc5eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2921a3fe5SJan Luebbe /* 3921a3fe5SJan Luebbe * AURORA shared L2 cache controller support 4921a3fe5SJan Luebbe * 5921a3fe5SJan Luebbe * Copyright (C) 2012 Marvell 6921a3fe5SJan Luebbe * 7921a3fe5SJan Luebbe * Yehuda Yitschak <yehuday@marvell.com> 8921a3fe5SJan Luebbe * Gregory CLEMENT <gregory.clement@free-electrons.com> 9921a3fe5SJan Luebbe */ 10921a3fe5SJan Luebbe 11921a3fe5SJan Luebbe #ifndef __ASM_ARM_HARDWARE_AURORA_L2_H 12921a3fe5SJan Luebbe #define __ASM_ARM_HARDWARE_AURORA_L2_H 13921a3fe5SJan Luebbe 14921a3fe5SJan Luebbe #define AURORA_SYNC_REG 0x700 15921a3fe5SJan Luebbe #define AURORA_RANGE_BASE_ADDR_REG 0x720 16921a3fe5SJan Luebbe #define AURORA_FLUSH_PHY_ADDR_REG 0x7f0 17921a3fe5SJan Luebbe #define AURORA_INVAL_RANGE_REG 0x774 18921a3fe5SJan Luebbe #define AURORA_CLEAN_RANGE_REG 0x7b4 19921a3fe5SJan Luebbe #define AURORA_FLUSH_RANGE_REG 0x7f4 20921a3fe5SJan Luebbe 21921a3fe5SJan Luebbe #define AURORA_ACR_REPLACEMENT_OFFSET 27 22921a3fe5SJan Luebbe #define AURORA_ACR_REPLACEMENT_MASK \ 23921a3fe5SJan Luebbe (0x3 << AURORA_ACR_REPLACEMENT_OFFSET) 24921a3fe5SJan Luebbe #define AURORA_ACR_REPLACEMENT_TYPE_WAYRR \ 25921a3fe5SJan Luebbe (0 << AURORA_ACR_REPLACEMENT_OFFSET) 26921a3fe5SJan Luebbe #define AURORA_ACR_REPLACEMENT_TYPE_LFSR \ 27921a3fe5SJan Luebbe (1 << AURORA_ACR_REPLACEMENT_OFFSET) 28921a3fe5SJan Luebbe #define AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU \ 29921a3fe5SJan Luebbe (3 << AURORA_ACR_REPLACEMENT_OFFSET) 30921a3fe5SJan Luebbe 310770bc92SJan Luebbe #define AURORA_ACR_PARITY_EN (1 << 21) 320770bc92SJan Luebbe #define AURORA_ACR_ECC_EN (1 << 20) 330770bc92SJan Luebbe 34921a3fe5SJan Luebbe #define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET 0 35921a3fe5SJan Luebbe #define AURORA_ACR_FORCE_WRITE_POLICY_MASK \ 36921a3fe5SJan Luebbe (0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET) 37921a3fe5SJan Luebbe #define AURORA_ACR_FORCE_WRITE_POLICY_DIS \ 38921a3fe5SJan Luebbe (0 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET) 39921a3fe5SJan Luebbe #define AURORA_ACR_FORCE_WRITE_BACK_POLICY \ 40921a3fe5SJan Luebbe (1 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET) 41921a3fe5SJan Luebbe #define AURORA_ACR_FORCE_WRITE_THRO_POLICY \ 42921a3fe5SJan Luebbe (2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET) 43921a3fe5SJan Luebbe 440770bc92SJan Luebbe #define AURORA_ERR_CNT_REG 0x600 450770bc92SJan Luebbe #define AURORA_ERR_ATTR_CAP_REG 0x608 460770bc92SJan Luebbe #define AURORA_ERR_ADDR_CAP_REG 0x60c 470770bc92SJan Luebbe #define AURORA_ERR_WAY_CAP_REG 0x610 480770bc92SJan Luebbe #define AURORA_ERR_INJECT_CTL_REG 0x614 490770bc92SJan Luebbe #define AURORA_ERR_INJECT_MASK_REG 0x618 500770bc92SJan Luebbe 510770bc92SJan Luebbe #define AURORA_ERR_CNT_CLR_OFFSET 31 520770bc92SJan Luebbe #define AURORA_ERR_CNT_CLR \ 530770bc92SJan Luebbe (0x1 << AURORA_ERR_CNT_CLR_OFFSET) 540770bc92SJan Luebbe #define AURORA_ERR_CNT_UE_OFFSET 16 550770bc92SJan Luebbe #define AURORA_ERR_CNT_UE_MASK \ 560770bc92SJan Luebbe (0x7fff << AURORA_ERR_CNT_UE_OFFSET) 570770bc92SJan Luebbe #define AURORA_ERR_CNT_CE_OFFSET 0 580770bc92SJan Luebbe #define AURORA_ERR_CNT_CE_MASK \ 590770bc92SJan Luebbe (0xffff << AURORA_ERR_CNT_CE_OFFSET) 600770bc92SJan Luebbe 610770bc92SJan Luebbe #define AURORA_ERR_ATTR_SRC_OFF 16 620770bc92SJan Luebbe #define AURORA_ERR_ATTR_SRC_MSK \ 630770bc92SJan Luebbe (0x7 << AURORA_ERR_ATTR_SRC_OFF) 640770bc92SJan Luebbe #define AURORA_ERR_ATTR_TXN_OFF 12 650770bc92SJan Luebbe #define AURORA_ERR_ATTR_TXN_MSK \ 660770bc92SJan Luebbe (0xf << AURORA_ERR_ATTR_TXN_OFF) 670770bc92SJan Luebbe #define AURORA_ERR_ATTR_ERR_OFF 8 680770bc92SJan Luebbe #define AURORA_ERR_ATTR_ERR_MSK \ 690770bc92SJan Luebbe (0x3 << AURORA_ERR_ATTR_ERR_OFF) 700770bc92SJan Luebbe #define AURORA_ERR_ATTR_CAP_VALID_OFF 0 710770bc92SJan Luebbe #define AURORA_ERR_ATTR_CAP_VALID \ 720770bc92SJan Luebbe (0x1 << AURORA_ERR_ATTR_CAP_VALID_OFF) 730770bc92SJan Luebbe 740770bc92SJan Luebbe #define AURORA_ERR_ADDR_CAP_ADDR_MASK 0xffffffe0 750770bc92SJan Luebbe 760770bc92SJan Luebbe #define AURORA_ERR_WAY_IDX_OFF 8 770770bc92SJan Luebbe #define AURORA_ERR_WAY_IDX_MSK \ 780770bc92SJan Luebbe (0xfff << AURORA_ERR_WAY_IDX_OFF) 790770bc92SJan Luebbe #define AURORA_ERR_WAY_CAP_WAY_OFFSET 1 800770bc92SJan Luebbe #define AURORA_ERR_WAY_CAP_WAY_MASK \ 810770bc92SJan Luebbe (0xf << AURORA_ERR_WAY_CAP_WAY_OFFSET) 820770bc92SJan Luebbe 830770bc92SJan Luebbe #define AURORA_ERR_INJECT_CTL_ADDR_MASK 0xfffffff0 840770bc92SJan Luebbe #define AURORA_ERR_ATTR_TXN_OFF 12 850770bc92SJan Luebbe #define AURORA_ERR_INJECT_CTL_EN_MASK 0x3 860770bc92SJan Luebbe #define AURORA_ERR_INJECT_CTL_EN_PARITY 0x2 870770bc92SJan Luebbe #define AURORA_ERR_INJECT_CTL_EN_ECC 0x1 880770bc92SJan Luebbe 891a85cb4bSJan Luebbe #define AURORA_MAX_RANGE_SIZE 1024 90921a3fe5SJan Luebbe 91921a3fe5SJan Luebbe #define AURORA_WAY_SIZE_SHIFT 2 92921a3fe5SJan Luebbe 93921a3fe5SJan Luebbe #define AURORA_CTRL_FW 0x100 94921a3fe5SJan Luebbe 95921a3fe5SJan Luebbe /* chose a number outside L2X0_CACHE_ID_PART_MASK to be sure to make 96921a3fe5SJan Luebbe * the distinction between a number coming from hardware and a number 97921a3fe5SJan Luebbe * coming from the device tree */ 98921a3fe5SJan Luebbe #define AURORA_CACHE_ID 0x100 99921a3fe5SJan Luebbe 100921a3fe5SJan Luebbe #endif /* __ASM_ARM_HARDWARE_AURORA_L2_H */ 101