Lines Matching +full:0 +full:xfffffff0
10 #define MMU_PTEH 0xFFFFFFF0 /* Page table entry register HIGH */
11 #define MMU_PTEL 0xFFFFFFF4 /* Page table entry register LOW */
12 #define MMU_TTB 0xFFFFFFF8 /* Translation table base register */
13 #define MMU_TEA 0xFFFFFFFC /* TLB Exception Address */
15 #define MMUCR 0xFFFFFFE0 /* MMU Control Register */
18 #define MMU_TLB_ADDRESS_ARRAY 0xF2000000
19 #define MMU_PAGE_ASSOC_BIT 0x80
23 #define MMU_CONTROL_INIT 0x007 /* SV=0, TF=1, IX=1, AT=1 */
25 #define TRA 0xffffffd0
26 #define EXPEVT 0xffffffd4
36 #define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */
38 #define INTEVT 0xffffffd8