Lines Matching +full:0 +full:xfffffff0

41 	mov	r0, #0
42 	mcr	p15, 0, r0, c15, c1, 2		@ Enable clock switching
43 	mcr	p15, 0, r0, c9, c0, 5		@ Allow read-buffer operations from userland
55 	mcr	p15, 0, ip, c15, c2, 2		@ Disable clock switching
56 	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
57 	bic	r0, r0, #0x1000			@ ...i............
58 	bic	r0, r0, #0x000e			@ ............wca.
59 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
75 	mov	ip, #0
76 	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
77 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
79 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
81 	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
82 	bic	ip, ip, #0x000f			@ ............wcam
83 	bic	ip, ip, #0x1100			@ ...i...s........
84 	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
95  *   0 = slow idle
108 	mov	r0, #0
111 	mcr	p15, 0, r0, c15, c2, 2		@ disable clock switching
112 	ldr	r1, [r1, #0]			@ force switch to MCLK
113 	mcr	p15, 0, r0, c15, c8, 2		@ wait for interrupt
115 	mcr	p15, 0, r0, c15, c1, 2		@ enable clock switching
131 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
152 	mcr	p15, 0, ip, c9, c0, 0		@ invalidate RB
153 	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
154 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
169 	armv3_set_pte_ext wc_disable=0
171 	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
172 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
182 	mrc	p15, 0, r4, c3, c0, 0		@ domain ID
183 	mrc	p15, 0, r5, c13, c0, 0		@ PID
184 	mrc	p15, 0, r6, c1, c0, 0		@ control reg
191 	mov	ip, #0
192 	mcr	p15, 0, ip, c8, c7, 0		@ flush I+D TLBs
193 	mcr	p15, 0, ip, c7, c7, 0		@ flush I&D cache
194 	mcr	p15, 0, ip, c9, c0, 0		@ invalidate RB
195 	mcr	p15, 0, ip, c9, c0, 5		@ allow user space to use RB
197 	mcr	p15, 0, r4, c3, c0, 0		@ domain ID
198 	mcr	p15, 0, r1, c2, c0, 0		@ translation table base addr
199 	mcr	p15, 0, r5, c13, c0, 0		@ PID
207 	mov	r0, #0
208 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
209 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
211 	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
215 	mrc	p15, 0, r0, c1, c0		@ get control register v4
229 	crval	clear=0x00003f3f, mmuset=0x0000313d, ucset=0x00001130
276 	sa1100_proc_info sa1100, 0x4401a110, 0xfffffff0, cpu_sa1100_name
277 	sa1100_proc_info sa1110, 0x6901b110, 0xfffffff0, cpu_sa1110_name