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/freebsd/sys/dev/mthca/
H A Dmthca_eq.c44 MTHCA_NUM_ASYNC_EQE = 0x80,
45 MTHCA_NUM_CMD_EQE = 0x80,
46 MTHCA_NUM_SPARE_EQE = 0x80,
47 MTHCA_EQ_ENTRY_SIZE = 0x20
68 #define MTHCA_EQ_STATUS_OK ( 0 << 28)
71 #define MTHCA_EQ_OWNER_SW ( 0 << 24)
81 MTHCA_EVENT_TYPE_COMP = 0x00,
82 MTHCA_EVENT_TYPE_PATH_MIG = 0x01,
83 MTHCA_EVENT_TYPE_COMM_EST = 0x02,
84 MTHCA_EVENT_TYPE_SQ_DRAINED = 0x03,
[all …]
/freebsd/sys/dev/mlx4/
H A Dcq.h96 MLX4_CQE_QPN_MASK = 0xffffff,
97 MLX4_CQE_VID_MASK = 0xfff,
101 MLX4_CQE_OWNER_MASK = 0x80,
102 MLX4_CQE_IS_SEND_MASK = 0x40,
103 MLX4_CQE_OPCODE_MASK = 0x1f
107 MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR = 0x01,
108 MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR = 0x02,
109 MLX4_CQE_SYNDROME_LOCAL_PROT_ERR = 0x04,
110 MLX4_CQE_SYNDROME_WR_FLUSH_ERR = 0x05,
111 MLX4_CQE_SYNDROME_MW_BIND_ERR = 0x06,
[all …]
/freebsd/contrib/ofed/libmlx5/
H A Dcq.c49 CQ_OK = 0,
55 MLX5_CQ_MODIFY_RESEIZE = 0,
68 return (cqe->l4_hdr_type_etc >> 2) & 0x3; in get_cqe_l3_hdr_type()
103 cq->dbrec[MLX5_CQ_SET_CI] = htobe32(cq->cons_index & 0xffffff); in update_cons_index()
191 int err = 0; in handle_responder()
251 wc->sl = (be32toh(cqe->flags_rqpn) >> 24) & 0xf; in handle_responder()
252 wc->src_qp = be32toh(cqe->flags_rqpn) & 0xffffff; in handle_responder()
253 wc->dlid_path_bits = cqe->ml_path & 0x7f; in handle_responder()
255 wc->wc_flags |= g ? IBV_WC_GRH : 0; in handle_responder()
256 wc->pkey_index = be32toh(cqe->imm_inval_pkey) & 0xffff; in handle_responder()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dgpio-stp-xway.yaml20 pattern: "^gpio@[0-9a-f]+$"
41 minimum: 0x000000
42 maximum: 0xffffff
49 minimum: 0x0
50 maximum: 0x7
57 minimum: 0x0
58 maximum: 0x3
71 minimum: 0x0
72 maximum: 0x7
86 reg = <0xE100BB0 0x40>;
[all …]
/freebsd/contrib/ofed/opensm/opensm/
H A Dosm_inform.c230 #if 0 in osm_infr_insert_to_db()
252 " Enum:0x%X from Database\n", in osm_infr_remove_from_db()
312 static atomic32_t trap_fwd_trans_id = 0x02DAB000; in send_report()
323 " to InformInfo LID %u GUID 0x%" PRIx64 ", TID 0x%X\n", in send_report()
346 (uint64_t) (0xFFFFFFFF)); in send_report()
347 if (trap_fwd_trans_id == 0) in send_report()
349 (uint64_t) (0xFFFFFFFF)); in send_report()
352 tid, IB_MAD_ATTR_NOTICE, 0); in send_report()
427 "MGID %s and port GUID:0x%016" PRIx64 " do not share same pkey\n", in is_access_permitted()
439 "Cannot find source port with GUID:0x%016" PRIx64 "\n", in is_access_permitted()
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Discsi_common.h42 #define ISCSI_DEFAULT_HEADER_DIGEST (0)
43 #define ISCSI_DEFAULT_DATA_DIGEST (0)
46 #define ISCSI_DEFAULT_MAX_PDU_LENGTH (0x2000)
47 #define ISCSI_DEFAULT_FIRST_BURST_LENGTH (0x10000)
48 #define ISCSI_DEFAULT_MAX_BURST_LENGTH (0x40000)
52 #define ISCSI_MIN_VAL_MAX_PDU_LENGTH (0x200)
53 #define ISCSI_MAX_VAL_MAX_PDU_LENGTH (0xffffff)
54 #define ISCSI_MIN_VAL_BURST_LENGTH (0x200)
55 #define ISCSI_MAX_VAL_BURST_LENGTH (0xffffff)
57 #define ISCSI_MAX_VAL_MAX_OUTSTANDING_R2T (0xff) // 0x10000 according to RFC
[all …]
H A Decore_hsi_debug_tools.h37 GRCBASE_GRC = 0x50000,
38 GRCBASE_MISCS = 0x9000,
39 GRCBASE_MISC = 0x8000,
40 GRCBASE_DBU = 0xa000,
41 GRCBASE_PGLUE_B = 0x2a8000,
42 GRCBASE_CNIG = 0x218000,
43 GRCBASE_CPMU = 0x30000,
44 GRCBASE_NCSI = 0x40000,
45 GRCBASE_OPTE = 0x53000,
46 GRCBASE_BMB = 0x540000,
[all …]
/freebsd/sys/dev/ixl/
H A Di40e_register.h38 #define I40E_GL_ARQBAH 0x000801C0 /* Reset: EMPR */
39 #define I40E_GL_ARQBAH_ARQBAH_SHIFT 0
40 #define I40E_GL_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ARQBAH_ARQBAH_SHIFT)
41 #define I40E_GL_ARQBAL 0x000800C0 /* Reset: EMPR */
42 #define I40E_GL_ARQBAL_ARQBAL_SHIFT 0
43 #define I40E_GL_ARQBAL_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ARQBAL_ARQBAL_SHIFT)
44 #define I40E_GL_ARQH 0x000803C0 /* Reset: EMPR */
45 #define I40E_GL_ARQH_ARQH_SHIFT 0
46 #define I40E_GL_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_GL_ARQH_ARQH_SHIFT)
47 #define I40E_GL_ARQT 0x000804C0 /* Reset: EMPR */
[all …]
/freebsd/sys/dev/mlx5/
H A Dcq.h54 MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR = 0x01,
55 MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR = 0x02,
56 MLX5_CQE_SYNDROME_LOCAL_PROT_ERR = 0x04,
57 MLX5_CQE_SYNDROME_WR_FLUSH_ERR = 0x05,
58 MLX5_CQE_SYNDROME_MW_BIND_ERR = 0x06,
59 MLX5_CQE_SYNDROME_BAD_RESP_ERR = 0x10,
60 MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR = 0x11,
61 MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12,
62 MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR = 0x13,
63 MLX5_CQE_SYNDROME_REMOTE_OP_ERR = 0x1
[all...]
H A Dfs.h58 MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT = BIT(0),
67 MLX5_FS_DEFAULT_FLOW_TAG = 0xFFFFFF,
68 MLX5_FS_ETH_FLOW_TAG = 0xFFFFFE,
69 MLX5_FS_SNIFFER_FLOW_TAG = 0xFFFFFD,
73 MLX5_FLOW_RULE_FWD_ACTION_ALLOW = 0x1,
74 MLX5_FLOW_RULE_FWD_ACTION_DROP = 0x2,
75 MLX5_FLOW_RULE_FWD_ACTION_DEST = 0x4,
79 MLX5_FS_FLOW_TAG_MASK = 0xFFFFFF,
[all...]
/freebsd/sys/dev/mlx4/mlx4_core/
H A Dmlx4_fw.c73 } while (0)
85 } while (0)
90 [ 0] = "RC transport", in dump_dev_cap_flags()
125 for (i = 0; i < ARRAY_SIZE(fname); ++i) in dump_dev_cap_flags()
133 [0] = "RSS support", in dump_dev_cap_flags2()
172 for (i = 0; i < ARRAY_SIZE(fname); ++i) in dump_dev_cap_flags2()
181 int err = 0; in mlx4_MOD_STAT_CFG()
183 #define MOD_STAT_CFG_IN_SIZE 0x100 in mlx4_MOD_STAT_CFG()
185 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002 in mlx4_MOD_STAT_CFG()
186 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003 in mlx4_MOD_STAT_CFG()
[all …]
H A Dmlx4_eq.c51 MLX4_NUM_ASYNC_EQE = 0x100,
52 MLX4_NUM_SPARE_EQE = 0x80,
53 MLX4_EQ_ENTRY_SIZE = 0x20
56 #define MLX4_EQ_STATUS_OK ( 0 << 28)
58 #define MLX4_EQ_OWNER_SW ( 0 << 24)
99 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) | in eq_set_ci()
118 …return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % … in get_eqe()
124 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe; in next_eqe_sw()
131 return (!!(eqe->owner & 0x80) ^ in next_slave_event_eqe()
167 for (i = 0; i <= dev->persist->num_vfs; i++) { in mlx4_gen_slave_eqe()
[all …]
H A Dmlx4_mcg.c59 int err = 0; in mlx4_QP_FLOW_STEERING_ATTACH()
61 err = mlx4_cmd_imm(dev, mailbox->dma, &imm, size, 0, in mlx4_QP_FLOW_STEERING_ATTACH()
73 int err = 0; in mlx4_QP_FLOW_STEERING_DETACH()
75 err = mlx4_cmd(dev, regid, 0, 0, in mlx4_QP_FLOW_STEERING_DETACH()
85 return mlx4_cmd_box(dev, 0, mailbox->dma, index, 0, MLX4_CMD_READ_MCG, in mlx4_READ_ENTRY()
92 return mlx4_cmd(dev, mailbox->dma, index, 0, MLX4_CMD_WRITE_MCG, in mlx4_WRITE_ENTRY()
102 return mlx4_cmd(dev, mailbox->dma, in_mod, 0x1, in mlx4_WRITE_PROMISC()
113 err = mlx4_cmd_imm(dev, mailbox->dma, &imm, 0, op_mod, in mlx4_GID_HASH()
189 return 0; in new_steering_entry()
205 members_count = be32_to_cpu(mgm->members_count) & 0xffffff; in new_steering_entry()
[all …]
/freebsd/sys/dev/mlx5/mlx5_core/
H A Dmlx5_eq.c45 MLX5_EQE_OWNER_INIT_VAL = 0x1,
49 MLX5_NUM_SPARE_EQE = 0x80,
50 MLX5_NUM_ASYNC_EQE = 0x100,
55 MLX5_EQ_DOORBEL_OFFSET = 0x40,
91 u32 in[MLX5_ST_SZ_DW(destroy_eq_in)] = {0}; in mlx5_cmd_destroy_eq()
92 u32 out[MLX5_ST_SZ_DW(destroy_eq_out)] = {0}; in mlx5_cmd_destroy_eq()
214 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2); in eq_update_ci()
215 u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24); in eq_update_ci()
234 int eqes_found = 0; in mlx5_eq_int()
235 int set_ci = 0; in mlx5_eq_int()
[all …]
/freebsd/contrib/ofed/libmlx4/
H A Dcq.c48 MLX4_CQ_DOORBELL = 0x20
52 CQ_OK = 0,
62 MLX4_CQE_QPN_MASK = 0xffffff,
66 MLX4_CQE_OWNER_MASK = 0x80,
67 MLX4_CQE_IS_SEND_MASK = 0x40,
68 MLX4_CQE_OPCODE_MASK = 0x1f
72 MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR = 0x01,
73 MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR = 0x02,
74 MLX4_CQE_SYNDROME_LOCAL_PROT_ERR = 0x04,
75 MLX4_CQE_SYNDROME_WR_FLUSH_ERR = 0x05,
[all …]
/freebsd/sys/dev/dcons/
H A Ddcons_crom.c68 static int force_console = 0;
71 #define ADDR_HI(x) (((x) >> 24) & 0xffffff)
72 #define ADDR_LO(x) ((x) & 0xffffff)
88 BUS_ADD_CHILD(parent, 0, "dcons_crom", device_get_unit(parent)); in dcons_crom_identify()
102 return (0); in dcons_crom_probe()
157 sc->bus_addr = segments[0].ds_addr; in dmamap_cb()
161 "bus_addr 0x%jx\n", (uintmax_t)sc->bus_addr); in dmamap_cb()
162 if (dcons_paddr != 0) { in dmamap_cb()
202 /*boundary*/ 0, in dcons_crom_attach()
213 if (error != 0) in dcons_crom_attach()
[all …]
/freebsd/stand/i386/isoboot/
H A Disoboot.c42 #define ARGS 0x900
45 #define MEM_BASE 0x12
46 #define MEM_EXT 0x15
48 #define DRV_HARD 0x80
49 #define DRV_MASK 0x7f
51 #define TYPE_AD 0
116 return (0); in xfsread()
125 v86.ebx = 0; in bios_getmem()
128 v86.addr = MEM_EXT; /* int 0x15 function 0xe820*/ in bios_getmem()
129 v86.eax = 0xe820; in bios_getmem()
[all …]
/freebsd/contrib/wpa/src/common/
H A Dtnc.h76 #define TNC_RESULT_SUCCESS 0
88 #define TNC_CONNECTION_STATE_CREATE 0
95 #define TNC_VENDORID_ANY ((TNC_VendorID) 0xffffff)
96 #define TNC_SUBTYPE_ANY ((TNC_Subtype) 0xff)
99 #define TNC_TNCCS_RECOMMENDATION 0x00000001
100 #define TNC_TNCCS_ERROR 0x00000002
101 #define TNC_TNCCS_PREFERREDLANGUAGE 0x00000003
102 #define TNC_TNCCS_REASONSTRINGS 0x00000004
/freebsd/contrib/file/magic/Magdir/
H A Dplaydate15 0 string Playdate\ IMG Playdate image data
16 >12 belong&0x80 0x80 (compressed)
19 >12 belong&0x80 0x00 (uncompressed)
24 0 string Playdate\ IMT Playdate image data set
25 >12 belong&0x80 0x80 (compressed)
29 >12 belong&0x80 0x00 (uncompressed)
34 0 string Playdate\ STR Playdate localization strings
35 >12 belong&0x80 0x80 (compressed)
36 >12 belong&0x80 0x00 (uncompressed)
39 0 string Playdate\ AUD Playdate audio file
[all …]
/freebsd/sys/arm/nvidia/drm2/
H A Dtegra_hdmi_reg.h35 #define HDMI_NV_PDISP_SOR_STATE0 0x001
36 #define SOR_STATE0_UPDATE (1 << 0)
38 #define HDMI_NV_PDISP_SOR_STATE1 0x002
41 #define SOR_STATE1_ASY_HEAD_OPMODE(x) (((x) & 0x3) << 0)
42 #define ASY_HEAD_OPMODE_SLEEP 0
46 #define HDMI_NV_PDISP_SOR_STATE2 0x003
50 #define SOR_STATE2_ASY_PROTOCOL(x) (((x) & 0xf) << 8)
53 #define SOR_STATE2_ASY_CRCMODE(x) (((x) & 0x3) << 6)
54 #define ASY_CRCMODE_ACTIVE 0
57 #define SOR_STATE2_ASY_SUBOWNER(x) (((x) & 0x3) << 4)
[all …]
/freebsd/sys/dev/cxgbe/common/
H A Dt4_hw.h42 EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */
107 #define S_QSTAT_PIDX 0
108 #define M_QSTAT_PIDX 0xffff
112 #define M_QSTAT_CIDX 0xffff
131 #define S_RSPD_LEN 0
132 #define M_RSPD_LEN 0x7fffffff
150 #define M_RSPD_TYPE 0x3
155 #define S_QINTR_CNT_EN 0
160 #define M_QINTR_TIMER_IDX 0x7
174 #define S_PPOD_COLOR 0
[all …]
/freebsd/sys/contrib/libsodium/src/libsodium/crypto_pwhash/argon2/
H A Dargon2.h25 #define ARGON2_MAX_LANES UINT32_C(0xFFFFFF)
29 #define ARGON2_MAX_THREADS UINT32_C(0xFFFFFF)
36 #define ARGON2_MAX_OUTLEN UINT32_C(0xFFFFFFFF)
47 ARGON2_MIN(UINT32_C(0xFFFFFFFF), UINT64_C(1) << ARGON2_MAX_MEMORY_BITS)
51 #define ARGON2_MAX_TIME UINT32_C(0xFFFFFFFF)
54 #define ARGON2_MIN_PWD_LENGTH UINT32_C(0)
55 #define ARGON2_MAX_PWD_LENGTH UINT32_C(0xFFFFFFFF)
58 #define ARGON2_MIN_AD_LENGTH UINT32_C(0)
59 #define ARGON2_MAX_AD_LENGTH UINT32_C(0xFFFFFFFF)
63 #define ARGON2_MAX_SALT_LENGTH UINT32_C(0xFFFFFFFF)
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A Dnxp,tda998x.yaml24 default: 0x230145
25 maximum: 0xffffff
47 maximum: 0xff
50 enum: [ 0, 1 ]
66 port@0:
93 #size-cells = <0>;
97 reg = <0x70>;
100 video-ports = <0x230145>;
104 audio-ports = <TDA998x_SPDIF 0x0
[all...]
/freebsd/sys/dev/mlx5/mlx5_accel/
H A Dmlx5_ipsec_rxtx.c36 #define MLX5_IPSEC_METADATA_HANDLE(ipsec_metadata) (ipsec_metadata & 0xFFFFFF)
46 return (0); in mlx5_accel_ipsec_rx_tag_add()
48 return (0); in mlx5_accel_ipsec_rx_tag_add()
55 return (0); in mlx5_accel_ipsec_rx_tag_add()
/freebsd/sys/dev/qat/qat_common/
H A Dadf_gen4_pfvf.c12 #define ADF_4XXX_PF2VM_OFFSET(i) (0x40B010 + ((i)*0x20))
13 #define ADF_4XXX_VM2PF_OFFSET(i) (0x40B014 + ((i)*0x20))
16 #define ADF_4XXX_VM2PF_SOU 0x41A180
17 #define ADF_4XXX_VM2PF_MSK 0x41A1C0
18 #define ADF_GEN4_VF_MSK 0xFFFF
21 #define ADF_PFVF_GEN4_MSGTYPE_MASK 0x3F
23 #define ADF_PFVF_GEN4_MSGDATA_MASK 0xFFFFFF
25 #define ADF_4XXXIOV_PF2VM_OFFSET 0x100C
26 #define ADF_4XXXIOV_VM2PF_OFFSET 0x1008
70 if (ret < 0) in adf_gen4_pfvf_send()
[all …]

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