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Searched +full:0 +full:xfffffe00 (Results 1 – 18 of 18) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/rtc/
H A Datmel,at91rm9200-rtc.yaml50 reg = <0xfffffe00 0x100>;
/freebsd/sys/dev/ath/ath_hal/ar5416/
H A Dar5416_cal.c141 cal->calSamples = 0; in ar5416ResetMeasurement()
150 #if 0
167 ichan.calValid = 0;
168 for (i = 0; i < init_cal_count; i++) {
172 if (!ath_hal_wait(ah, AR_PHY_TIMING_CTRL4, AR_PHY_TIMING_CTRL4_DO_CAL, 0)) {
218 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { in ar5416InitCalHardware()
287 #if 0 in ar5416InitCal()
295 if (cal->ah_cal_curr != AH_NULL && !ar5416RunInitCals(ah, 0)) in ar5416InitCal()
327 ichan->calValid = 0; in ar5416InitCal()
350 "%s: invalid channel %u/0x%x; no mapping\n", in ar5416ResetCalValid()
[all …]
/freebsd/sys/dev/ath/ath_hal/ar9002/
H A Dar9287.c33 #define N(a) (sizeof(a)/sizeof(a[0]))
61 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
69 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
75 uint16_t bMode, fracMode, aModeRefSel = 0; in ar9287SetChannel()
76 uint32_t freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; in ar9287SetChannel()
86 reg32 &= 0xc0000000; in ar9287SetChannel()
90 int regWrites = 0; in ar9287SetChannel()
94 aModeRefSel = 0; in ar9287SetChannel()
95 channelSel = (freq * 0x10000)/15; in ar9287SetChannel()
[all …]
H A Dar9280.c33 #define N(a) (sizeof(a)/sizeof(a[0]))
61 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
69 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
75 uint16_t bMode, fracMode, aModeRefSel = 0; in ar9280SetChannel()
76 uint32_t freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; in ar9280SetChannel()
87 reg32 &= 0xc0000000; in ar9280SetChannel()
90 frac_n_5g = 0; in ar9280SetChannel()
97 aModeRefSel = 0; in ar9280SetChannel()
98 channelSel = (freq * 0x10000)/15; in ar9280SetChannel()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dat91rm9200.dtsi44 #size-cells = <0>;
46 cpu@0 {
49 reg = <0>;
55 reg = <0x20000000 0x04000000>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
74 reg = <0x00200000 0x4000>;
77 ranges = <0 0x00200000 0x4000>;
[all …]
H A Dat91sam9rl.dtsi43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0>;
54 reg = <0x20000000 0x04000000>;
60 #clock-cells = <0>;
61 clock-frequency = <0>;
66 #clock-cells = <0>;
67 clock-frequency = <0>;
72 #clock-cells = <0>;
79 reg = <0x00300000 0x10000>;
[all …]
H A Dat91sam9n12.dtsi42 #size-cells = <0>;
44 cpu@0 {
47 reg = <0>;
53 reg = <0x20000000 0x10000000>;
59 #clock-cells = <0>;
60 clock-frequency = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
72 reg = <0x00300000 0x8000>;
75 ranges = <0 0x00300000 0x8000>;
[all …]
H A Dat91sam9x5.dtsi44 #size-cells = <0>;
46 cpu@0 {
49 reg = <0>;
55 reg = <0x20000000 0x10000000>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
73 #clock-cells = <0>;
80 reg = <0x00300000 0x8000>;
[all …]
H A Dsama5d3.dtsi46 #size-cells = <0>;
47 cpu@0 {
50 reg = <0x0>;
56 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
61 reg = <0x20000000 0x8000000>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
73 #clock-cells = <0>;
74 clock-frequency = <0>;
79 #clock-cells = <0>;
[all …]
H A Dsam9x60.dtsi37 #size-cells = <0>;
39 cpu@0 {
42 reg = <0>;
48 reg = <0x20000000 0x10000000>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x00300000 0x100000>;
68 ranges = <0 0x00300000 0x100000>;
79 #size-cells = <0>;
81 reg = <0x00500000 0x100000
[all …]
/freebsd/sys/netpfil/ipfw/nat64/
H A Dnat64_translate.c117 static const int stealth_off = 0;
124 if (direct != 0) { in nat64_set_output_method()
145 return (V_nat64out == &nat64_direct ? 1: 0); in nat64_get_output_method()
166 if (error != 0) in nat64_direct_output()
186 error = 0; in nat64_direct_output_one()
217 if (error != 0) { in nat64_direct_output_one()
224 if (error != 0) in nat64_direct_output_one()
257 if (ret != 0) in nat64_output()
286 return (0); in nat64_check_prefixlen()
295 if (nat64_check_prefixlen(length) != 0) in nat64_check_prefix6()
[all …]
/freebsd/contrib/tcpdump/
H A Dutil-print.c58 enum date_flag { WITHOUT_DATE = 0, WITH_DATE = 1 };
59 enum time_flag { UTC_TIME = 0, LOCAL_TIME = 1 };
72 c ^= 0x40; /* DEL to ?, others to alpha */ in fn_print_char()
86 while (*s != '\0') { in fn_print_str()
108 * this will always be non-zero. Return 0 if truncated.
117 bytes = 0; in nd_printztn()
119 if (n == 0 || (ep != NULL && s >= ep)) { in nd_printztn()
130 bytes = 0; in nd_printztn()
138 if (c == '\0') { in nd_printztn()
160 while (n > 0 && (ep == NULL || s < ep)) { in nd_printn()
[all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
39 #define AlignPC(pc_val) (pc_val & 0xFFFFFFFC) in LLDB_PLUGIN_DEFINE_ADV()
47 ::memset(&reg_info, 0, sizeof(RegisterInfo)); in LLDB_PLUGIN_DEFINE_ADV()
234 // FPA Registers 0-7 in LLDB_PLUGIN_DEFINE_ADV()
260 // Intel wireless MMX general purpose registers 0 - 7 XScale accumulator in LLDB_PLUGIN_DEFINE_ADV()
261 // register 0 - 7 (they do overlap with wCGR0 - wCGR7) in LLDB_PLUGIN_DEFINE_ADV()
287 // Intel wireless MMX data registers 0 - 15 in LLDB_PLUGIN_DEFINE_ADV()
423 // Intel wireless MMX control register in co-processor 0 - 7 in LLDB_PLUGIN_DEFINE_ADV()
604 // Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition.
609 return 0; in CountITSize()
[all …]
/freebsd/sys/contrib/ncsw/Peripherals/FM/HC/
H A Dhc.c46 #define DEFAULT_dataMemId 0
48 #define HC_HCOR_OPCODE_PLCR_PRFL 0x0
49 #define HC_HCOR_OPCODE_KG_SCM 0x1
50 #define HC_HCOR_OPCODE_SYNC 0x2
51 #define HC_HCOR_OPCODE_CC 0x3
52 #define HC_HCOR_OPCODE_CC_AGE_MASK 0x4
53 #define HC_HCOR_OPCODE_CC_CAPWAP_REASSM_TIMEOUT 0x5
54 #define HC_HCOR_OPCODE_CC_REASSM_TIMEOUT 0x10
55 #define HC_HCOR_OPCODE_CC_IP_FRAG_INITIALIZATION 0x11
56 #define HC_HCOR_OPCODE_CC_UPDATE_WITH_AGING 0x13
[all …]
/freebsd/sys/dev/ichwd/
H A Dichwd.c50 * Intel swears it's always at offset 0x60, so we use that.
291 { 0, NULL, 0, 0 },
301 { 0, NULL, 0, 0 },
340 } while (0)
371 return ((ichwd_read_smi_4(sc, SMI_EN) & SMI_TCO_EN) != 0); in ichwd_smi_is_enabled()
383 * by writing a 1, not a 0. in ichwd_sts_reset()
422 sc->active = 0; in ichwd_tmr_disable()
454 tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff); in ichwd_tmr_set()
462 tmr_val16 &= (~TCO_RLD2_TMR_MAX & 0xffff); in ichwd_tmr_set()
478 int rc = 0; in ichwd_clear_noreboot()
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212_reset.c82 for (r = 0; r < ia->rows; r++) { in write_common()
83 uint32_t reg = V(r, 0); in write_common()
123 #define N(a) (sizeof (a) / sizeof (a[0])) in ar5212Reset()
124 #define FAIL(_code) do { ecode = _code; goto bad; } while (0) in ar5212Reset()
132 int16_t cckOfdmPwrDelta = 0; in ar5212Reset()
199 saveFrameSeqCount = 0; /* NB: silence compiler */ in ar5212Reset()
204 #if 0 in ar5212Reset()
238 if (saveDefAntenna == 0) /* XXX magic constants */ in ar5212Reset()
276 "%s: invalid channel %u/0x%x\n", in ar5212Reset()
288 "%s: invalid channel %u/0x%x\n", in ar5212Reset()
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_pcie_w_reg.h51 /* [0x0] */
53 /* [0x4] */
55 /* [0x8] */
58 /* [0x10] */
63 /* [0x0] */
65 /* [0x4] */
67 /* [0x8] */
70 /* [0x10] */
72 /* [0x14] */
74 /* [0x18] */
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_reset.c43 #if 0
83 volatile u_int32_t *usb_ctrl_r1 = (u_int32_t *) 0xb8116c84; \
84 volatile u_int32_t *usb_ctrl_r2 = (u_int32_t *) 0xb8116c88; \
85 *usb_ctrl_r1 = (*usb_ctrl_r1 & 0xffefffff); \
86 *usb_ctrl_r2 = (*usb_ctrl_r2 & 0xfc1fffff) | (1 << 21) | (3 << 22); \
88 } while (0)
111 (1 << 21) | (0xf << 22), in ar9300_disable_pll_lock_detect()
112 (1 << 21) | (0x3 << 22)); in ar9300_disable_pll_lock_detect()
178 ath_hal_getcapability(ah, HAL_CAP_MFP, 0, &mfpcap); in ar9300_init_mfp()
197 * Cisco spec defined bits 0-3 as mask in ar9300_init_mfp()
[all …]