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Searched +full:0 +full:xff900000 (Results 1 – 8 of 8) sorted by relevance

/linux/Documentation/devicetree/bindings/mtd/
H A Ddenali,nand.yaml141 reg = <0xff900000 0x20>, <0xffb80000 0x1000>;
142 interrupts = <0 144 4>;
148 #size-cells = <0>;
150 nand@0 {
151 reg = <0>;
/linux/arch/arm/boot/dts/calxeda/
H A Dhighbank.dts9 /memreserve/ 0x00000000 0x0001000;
19 #size-cells = <0>;
24 reg = <0x900>;
43 reg = <0x901>;
62 reg = <0x902>;
81 reg = <0x903>;
98 memory@0 {
101 reg = <0x00000000 0xff900000>;
105 ranges = <0x00000000 0x00000000 0xffffffff>;
109 reg = <0xfff00000 0x1000>;
[all …]
/linux/arch/m68k/include/asm/
H A Dbvme6000hw.h11 #define BVME_PIT_BASE 0xffa00000
47 #define BVME_RTC_BASE 0xff900000
86 #define BVME_I596_BASE 0xff100000
88 #define BVME_ETHIRQ_REG 0xff20000b
90 #define BVME_LOCAL_IRQ_STAT 0xff20000f
92 #define BVME_ETHERR 0x02
93 #define BVME_ABORT_STATUS 0x08
95 #define BVME_NCR53C710_BASE 0xff000000
97 #define BVME_SCC_A_ADDR 0xffb0000b
98 #define BVME_SCC_B_ADDR 0xffb00003
[all …]
/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi21 service_reserved: svcbuffer@0 {
23 reg = <0x0 0x0 0x0 0x1000000>;
24 alignment = <0x1000>;
31 #size-cells = <0>;
33 cpu0: cpu@0 {
38 reg = <0x0>;
46 reg = <0x1>;
54 reg = <0x2>;
62 reg = <0x3>;
86 #address-cells = <0x2>;
[all …]
/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi22 service_reserved: svcbuffer@0 {
24 reg = <0x0 0x0 0x0 0x2000000>;
25 alignment = <0x1000>;
32 #size-cells = <0>;
34 cpu0: cpu@0 {
38 reg = <0x0>;
45 reg = <0x1>;
52 reg = <0x2>;
59 reg = <0x3>;
77 #address-cells = <0x2>;
[all …]
/linux/arch/arm/mach-orion5x/
H A Dts78xx-setup.c33 #define TS78XX_FPGA_REGS_PHYS_BASE 0xe8000000
34 #define TS78XX_FPGA_REGS_VIRT_BASE IOMEM(0xff900000)
38 .id = 0,
65 .phy_addr = MV643XX_ETH_PHY_ADDR(0),
78 #define TS_RTC_CTRL (TS78XX_FPGA_REGS_PHYS_BASE + 0x808)
79 #define TS_RTC_DATA (TS78XX_FPGA_REGS_PHYS_BASE + 0x80c)
82 DEFINE_RES_MEM(TS_RTC_CTRL, 0x01),
83 DEFINE_RES_MEM(TS_RTC_DATA, 0x01),
97 if (ts78xx_fpga.supports.ts_rtc.init == 0) { in ts78xx_ts_rtc_load()
119 #define TS_NAND_CTRL (TS78XX_FPGA_REGS_VIRT_BASE + 0x800) /* VIRT */
[all …]
/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga.dtsi23 #size-cells = <0>;
26 cpu0: cpu@0 {
29 reg = <0>;
43 interrupts = <0 176 4>, <0 177 4>;
45 reg = <0xff111000 0x1000>,
46 <0xff113000 0x1000>;
53 reg = <0xfffed000 0x1000>,
54 <0xfffec100 0x100>;
73 reg = <0xffe01000 0x1000>;
74 interrupts = <0 104 4>,
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-base.dtsi51 #size-cells = <0>;
79 cpu_l0: cpu@0 {
82 reg = <0x0 0x0>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
101 reg = <0x0 0x1>;
108 i-cache-size = <0x8000>;
111 d-cache-size = <0x8000>;
120 reg = <0x0 0x2>;
127 i-cache-size = <0x8000>;
[all …]