Searched +full:0 +full:xff900000 (Results 1 – 5 of 5) sorted by relevance
141 reg = <0xff900000 0x20>, <0xffb80000 0x1000>;142 interrupts = <0 144 4>;148 #size-cells = <0>;150 nand@0 {151 reg = <0>;
9 /memreserve/ 0x00000000 0x0001000;19 #size-cells = <0>;24 reg = <0x900>;43 reg = <0x901>;62 reg = <0x902>;81 reg = <0x903>;98 memory@0 {101 reg = <0x00000000 0xff900000>;105 ranges = <0x00000000 0x00000000 0xffffffff>;109 reg = <0xfff00000 0x1000>;[all …]
11 #define BVME_PIT_BASE 0xffa0000047 #define BVME_RTC_BASE 0xff90000086 #define BVME_I596_BASE 0xff10000088 #define BVME_ETHIRQ_REG 0xff20000b90 #define BVME_LOCAL_IRQ_STAT 0xff20000f92 #define BVME_ETHERR 0x0293 #define BVME_ABORT_STATUS 0x0895 #define BVME_NCR53C710_BASE 0xff00000097 #define BVME_SCC_A_ADDR 0xffb0000b98 #define BVME_SCC_B_ADDR 0xffb00003[all …]
22 service_reserved: svcbuffer@0 {24 reg = <0x0 0x0 0x0 0x2000000>;25 alignment = <0x1000>;32 #size-cells = <0>;34 cpu0: cpu@0 {38 reg = <0x0>;45 reg = <0x1>;52 reg = <0x2>;59 reg = <0x3>;77 #address-cells = <0x2>;[all …]
33 #define TS78XX_FPGA_REGS_PHYS_BASE 0xe800000034 #define TS78XX_FPGA_REGS_VIRT_BASE IOMEM(0xff900000)38 .id = 0,65 .phy_addr = MV643XX_ETH_PHY_ADDR(0),78 #define TS_RTC_CTRL (TS78XX_FPGA_REGS_PHYS_BASE + 0x808)79 #define TS_RTC_DATA (TS78XX_FPGA_REGS_PHYS_BASE + 0x80c)82 DEFINE_RES_MEM(TS_RTC_CTRL, 0x01),83 DEFINE_RES_MEM(TS_RTC_DATA, 0x01),97 if (ts78xx_fpga.supports.ts_rtc.init == 0) { in ts78xx_ts_rtc_load()119 #define TS_NAND_CTRL (TS78XX_FPGA_REGS_VIRT_BASE + 0x800) /* VIRT */[all …]