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/linux/drivers/firmware/efi/libstub/
H A Dprintk.c35 * The position of the most-significant 0 bit gives us the length of in utf8_to_utf32()
38 for (clen = 0; cx & 0x80; ++clen) in utf8_to_utf32()
41 * If the 0 bit is in position 8, this is a valid single-octet in utf8_to_utf32()
42 * encoding. If the 0 bit is in position 7 or positions 1-3, the in utf8_to_utf32()
50 for (i = 0; i < clen; ++i) { in utf8_to_utf32()
52 cx = (*s8)[i] ^ 0x80; in utf8_to_utf32()
53 if (cx & 0xc0) in utf8_to_utf32()
63 if (c32 > 0x10ffff || in utf8_to_utf32()
64 (c32 & 0xf800) == 0xd800 || in utf8_to_utf32()
65 clen != (c32 >= 0x80) + (c32 >= 0x800) + (c32 >= 0x10000)) in utf8_to_utf32()
[all …]
H A Dvsprintf.c25 int i = 0; in skip_atoi()
28 i = i * 10 + *((*s)++) - '0'; in skip_atoi()
33 * put_dec_full4 handles numbers in the range 0 <= r < 10000.
34 * The multiplier 0xccd is round(2^15/10), and the approximation
35 * r/10 == (r * 0xccd) >> 15 is exact for all r < 16389.
42 for (i = 0; i < 3; i++) { in put_dec_full4()
43 unsigned int q = (r * 0xccd) >> 15; in put_dec_full4()
44 *--end = '0' + (r - q * 10); in put_dec_full4()
47 *--end = '0' + r; in put_dec_full4()
54 * The approximation x/10000 == (x * 0x346DC5D7) >> 43
[all …]
H A Defi-stub-helper.c63 buf[len - 1] = '\0'; in efi_parse_options()
134 if ((src->attributes & ~EFI_LOAD_OPTION_MASK) != 0) in efi_load_option_unpack()
145 } while (c != L'\0'); in efi_load_option_unpack()
192 if ((load_option->attributes & ~EFI_LOAD_OPTION_BOOT_MASK) != 0) in efi_apply_loadoptions_quirk()
313 status = efi_fn_call(&method, hash_log_extend_event, protocol, 0, in efi_measure_tagged_event()
321 efi_warn("Failed to measure data for event %d: 0x%lx\n", event, status); in efi_measure_tagged_event()
334 int options_bytes = 0, safe_options_bytes = 0; /* UTF-8 bytes */ in efi_convert_cmdline()
335 unsigned long cmdline_addr = 0; in efi_convert_cmdline()
341 if (options_size > 0) in efi_convert_cmdline()
353 if (c < 0x80) { in efi_convert_cmdline()
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dpmi8994.dtsi9 reg = <0x2 SPMI_USID>;
11 #size-cells = <0>;
15 reg = <0xc000>;
17 gpio-ranges = <&pmi8994_gpios 0 0 10>;
25 reg = <0xa000>;
27 gpio-ranges = <&pmi8994_mpps 0 0 4>;
36 reg = <0x3 SPMI_USID>;
38 #size-cells = <0>;
44 #size-cells = <0>;
56 reg = <0xd800>, <0xd900>;
[all …]
H A Dpm660l.dtsi39 reg = <0x2 SPMI_USID>;
41 #size-cells = <0>;
45 reg = <0x2400>;
46 interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
47 #thermal-sensor-cells = <0>;
52 reg = <0xc000>;
54 gpio-ranges = <&pm660l_gpios 0 0 12>;
63 reg = <0x3 SPMI_USID>;
65 #size-cells = <0>;
75 reg = <0xd800>, <0xd900>;
[all …]
H A Dpmi8998.dtsi8 reg = <0x2 SPMI_USID>;
10 #size-cells = <0>;
14 reg = <0x1000>;
16 interrupts = <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>,
17 <0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>,
18 <0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>,
19 <0x2 0x13 0x6 IRQ_TYPE_EDGE_RISING>;
34 reg = <0xc000>;
36 gpio-ranges = <&pmi8998_gpios 0 0 14>;
44 reg = <0x4500>;
[all …]
H A Dpmi8950.dtsi11 reg = <0x2 SPMI_USID>;
13 #size-cells = <0>;
17 reg = <0x3100>;
18 interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
20 #size-cells = <0>;
23 channel@0 {
62 reg = <0xa000>;
64 gpio-ranges = <&pmi8950_mpps 0 0 4>;
72 reg = <0xc000>;
74 gpio-ranges = <&pmi8950_gpios 0 0 2>;
[all …]
H A Dpm6150l.dtsi18 hysteresis = <0>;
24 hysteresis = <0>;
30 hysteresis = <0>;
41 reg = <0x4 SPMI_USID>;
43 #size-cells = <0>;
47 reg = <0x2400>;
48 interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
49 #thermal-sensor-cells = <0>;
54 reg = <0x3100>;
55 interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
[all …]
H A Dpm8150l.dtsi21 hysteresis = <0>;
27 hysteresis = <0>;
33 hysteresis = <0>;
44 reg = <0x4 SPMI_USID>;
46 #size-cells = <0>;
50 reg = <0x0800>;
57 reg = <0x2400>;
58 interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
61 #thermal-sensor-cells = <0>;
66 reg = <0x3100>;
[all …]
/linux/drivers/staging/media/atomisp/i2c/
H A Dmt9m114.h46 #define MISENSOR_FWBURST0 0x80
47 #define MISENSOR_FWBURST1 0x81
48 #define MISENSOR_FWBURST4 0x84
49 #define MISENSOR_FWBURST 0x88
51 #define MISENSOR_TOK_TERM 0xf000 /* terminating token for reg list */
52 #define MISENSOR_TOK_DELAY 0xfe00 /* delay token for reg list */
53 #define MISENSOR_TOK_FWLOAD 0xfd00 /* token indicating load FW */
54 #define MISENSOR_TOK_POLL 0xfc00 /* token indicating poll instruction */
55 #define MISENSOR_TOK_RMW 0x0010 /* RMW operation */
56 #define MISENSOR_TOK_MASK 0xfff0
[all …]
/linux/drivers/edac/
H A Digen6_edac.c51 #define TOM_OFFSET 0xa0
53 #define TOLUD_OFFSET 0xbc
55 #define CAPID_C_OFFSET 0xec
59 #define CAPID_E_OFFSET 0xf0
64 #define ERRSTS_OFFSET 0xc8
69 #define ERRCMD_OFFSET 0xca
76 #define IBECC_ACTIVATE_EN BIT(0)
88 #define MCHBAR_OFFSET 0x48
89 #define MCHBAR_EN BIT_ULL(0)
91 #define MCHBAR_SIZE 0x10000
[all …]
/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/
H A Dmmu.json4 "EventCode": "0xD800",
10 "EventCode": "0xd801",
16 "EventCode": "0xd802",
22 "EventCode": "0xd803",
28 "EventCode": "0xd804",
34 "EventCode": "0xd805",
40 "EventCode": "0xd806",
46 "EventCode": "0xd807",
52 "EventCode": "0xd808",
58 "EventCode": "0xd809",
[all …]
/linux/drivers/staging/media/meson/vdec/
H A Dhevc_regs.h9 #define HEVC_ASSIST_MMU_MAP_ADDR 0xc024
11 #define HEVC_ASSIST_MBOX1_CLR_REG 0xc1d4
12 #define HEVC_ASSIST_MBOX1_MASK 0xc1d8
14 #define HEVC_ASSIST_SCRATCH_0 0xc300
15 #define HEVC_ASSIST_SCRATCH_1 0xc304
16 #define HEVC_ASSIST_SCRATCH_2 0xc308
17 #define HEVC_ASSIST_SCRATCH_3 0xc30c
18 #define HEVC_ASSIST_SCRATCH_4 0xc310
19 #define HEVC_ASSIST_SCRATCH_5 0xc314
20 #define HEVC_ASSIST_SCRATCH_6 0xc318
[all …]
/linux/Documentation/devicetree/bindings/leds/backlight/
H A Dqcom-wled.yaml66 minimum: 0
73 minimum: 0
111 Array of the WLED strings numbered from 0 to 3. Each
148 0 - Modulator A
152 enum: [ 0, 1 ]
153 default: 0
159 0 - CABC disabled
165 enum: [ 0, 1, 2, 3 ]
225 minimum: 0
229 minimum: 0
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dpm8941.dtsi11 polling-delay = <0>;
39 pm8941_0: pm8941@0 {
41 reg = <0x0 SPMI_USID>;
43 #size-cells = <0>;
47 reg = <0x6000>,
48 <0x6100>;
50 interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
55 reg = <0x800>;
59 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
66 interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
[all …]
/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereone/
H A Dcore-imp-def.json4 "EventCode": "0x10A",
10 "EventCode": "0x10B",
16 "EventCode": "0x110",
22 "EventCode": "0x111",
28 "EventCode": "0x112",
34 "EventCode": "0x113",
40 "EventCode": "0x114",
46 "EventCode": "0x115",
52 "EventCode": "0x116",
58 "EventCode": "0x117",
[all …]
/linux/drivers/net/wireless/mediatek/mt7601u/
H A Dinit.c94 mt7601u_wr(dev, MT_USB_DMA_CFG, 0); in mt7601u_reset_csr_bbp()
96 mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0); in mt7601u_reset_csr_bbp()
142 for (i = 0; i < 16; i++) { in mt76_init_beacon_offsets()
148 for (i = 0; i < 4; i++) in mt76_init_beacon_offsets()
167 mt7601u_wr(dev, MT_AUX_CLK_CFG, 0); in mt7601u_write_mac_initvals()
169 return 0; in mt7601u_write_mac_initvals()
181 for (i = 0; i < N_WCIDS; i++) { in mt7601u_init_wcid_mem()
182 vals[i * 2] = 0xffffffff; in mt7601u_init_wcid_mem()
183 vals[i * 2 + 1] = 0x00ffffff; in mt7601u_init_wcid_mem()
210 for (i = 0; i < N_WCIDS * 2; i++) in mt7601u_init_wcid_attr_mem()
[all …]
/linux/drivers/gpu/drm/panel/
H A Dpanel-orisetech-otm8009a.c25 #define MCS_ADRSFT 0x0000 /* Address Shift Function */
26 #define MCS_PANSET 0xB3A6 /* Panel Type Setting */
27 #define MCS_SD_CTRL 0xC0A2 /* Source Driver Timing Setting */
28 #define MCS_P_DRV_M 0xC0B4 /* Panel Driving Mode */
29 #define MCS_OSC_ADJ 0xC181 /* Oscillator Adjustment for Idle/Normal mode */
30 #define MCS_RGB_VID_SET 0xC1A1 /* RGB Video Mode Setting */
31 #define MCS_SD_PCH_CTRL 0xC480 /* Source Driver Precharge Control */
32 #define MCS_NO_DOC1 0xC48A /* Command not documented */
33 #define MCS_PWR_CTRL1 0xC580 /* Power Control Setting 1 */
34 #define MCS_PWR_CTRL2 0xC590 /* Power Control Setting 2 for Normal Mode */
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dcikd.h27 #define MC_SEQ_MISC0__MT__MASK 0xf0000000
28 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000
29 #define MC_SEQ_MISC0__MT__DDR2 0x20000000
30 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000
31 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000
32 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000
33 #define MC_SEQ_MISC0__MT__HBM 0x60000000
34 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000
39 #define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c)
40 #define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c)
[all …]
/linux/drivers/gpu/drm/i915/
H A Dintel_uncore.c67 uncore->debug->unclaimed_mmio_check = 0; in mmio_debug_suspend()
116 if (id >= 0 && id < FW_DOMAIN_ID_COUNT) in intel_uncore_forcewake_domain_to_str()
138 fw_clear(d, 0xefff); in fw_domain_reset()
140 fw_clear(d, 0xffff); in fw_domain_reset()
168 return __wait_for_ack(d, ack, 0); in wait_ack_clear()
184 if (fw_ack(d) == ~0) { in fw_domain_wait_ack_clear()
186 "%s: MMIO unreliable (forcewake register returns 0xFFFFFFFF)!\n", in fw_domain_wait_ack_clear()
199 ACK_CLEAR = 0,
208 const u32 value = type == ACK_SET ? ack_bit : 0; in fw_domain_wait_ack_with_fallback()
241 "%s had to use fallback to %s ack, 0x%x (passes %u)\n", in fw_domain_wait_ack_with_fallback()
[all …]
/linux/fs/unicode/
H A Dutf8-norm.c13 while (i >= 0 && um->tables->utf8agetab[i] != 0) { in utf8version_is_supported()
18 return 0; in utf8version_is_supported()
28 * 0x00000000 0x0000007F: 0xxxxxxx
29 * 0x00000000 0x000007FF: 110xxxxx 10xxxxxx
30 * 0x00000000 0x0000FFFF: 1110xxxx 10xxxxxx 10xxxxxx
31 * 0x00000000 0x001FFFFF: 11110xxx 10xxxxxx 10xxxxxx 10xxxxxx
32 * 0x00000000 0x03FFFFFF: 111110xx 10xxxxxx 10xxxxxx 10xxxxxx 10xxxxxx
33 * 0x00000000 0x7FFFFFFF: 1111110x 10xxxxxx 10xxxxxx 10xxxxxx 10xxxxxx 10xxxxxx
40 * 0x00000000 0x0000007F: 0xxxxxxx
41 * 0x00000080 0x000007FF: 110xxxxx 10xxxxxx
[all …]
H A Dmkutf8data.c50 int verbose = 0;
63 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
98 return 0; in age_valid()
100 return 0; in age_valid()
102 return 0; in age_valid()
119 * if offlen == 0 (non-branching node)
124 * if offlen != 0 (branching node)
133 #define BITNUM 0x07
134 #define NEXTBYTE 0x08
135 #define OFFLEN 0x30
[all …]
/linux/drivers/gpu/drm/bridge/
H A Dlontium-lt9211.c31 #define REG_PAGE_CONTROL 0xff
32 #define REG_CHIPID0 0x8100
33 #define REG_CHIPID0_VALUE 0x18
34 #define REG_CHIPID1 0x8101
35 #define REG_CHIPID1_VALUE 0x01
36 #define REG_CHIPID2 0x8102
37 #define REG_CHIPID2_VALUE 0xe3
39 #define REG_DSI_LANE 0xd000
40 /* DSI lane count - 0 means 4 lanes ; 1, 2, 3 means 1, 2, 3 lanes. */
56 regmap_reg_range(0xff, 0xff),
[all …]
/linux/drivers/net/ethernet/realtek/
H A Dr8169_phy_config.c23 int oldpage = phy_select_page(phydev, 0x0007); in r8168d_modify_extpage()
25 __phy_write(phydev, 0x1e, extpage); in r8168d_modify_extpage()
28 phy_restore_page(phydev, oldpage, 0); in r8168d_modify_extpage()
34 int oldpage = phy_select_page(phydev, 0x0005); in r8168d_phy_param()
36 __phy_write(phydev, 0x05, parm); in r8168d_phy_param()
37 __phy_modify(phydev, 0x06, mask, val); in r8168d_phy_param()
39 phy_restore_page(phydev, oldpage, 0); in r8168d_phy_param()
45 int oldpage = phy_select_page(phydev, 0x0a43); in r8168g_phy_param()
47 __phy_write(phydev, 0x13, parm); in r8168g_phy_param()
48 __phy_modify(phydev, 0x14, mask, val); in r8168g_phy_param()
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dnid.h33 #define CAYMAN_MAX_BACKENDS_MASK 0xFF
34 #define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF
36 #define CAYMAN_MAX_SIMDS_MASK 0xFFFF
37 #define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF
39 #define CAYMAN_MAX_PIPES_MASK 0xFF
40 #define CAYMAN_MAX_LDS_NUM 0xFFFF
42 #define CAYMAN_MAX_TCC_MASK 0xFF
44 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
45 #define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001
47 #define DMIF_ADDR_CONFIG 0xBD4
[all …]

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