31 #define REG_PAGE_CONTROL			0xff
32 #define REG_CHIPID0				0x8100
33 #define REG_CHIPID0_VALUE			0x18
34 #define REG_CHIPID1				0x8101
35 #define REG_CHIPID1_VALUE			0x01
36 #define REG_CHIPID2				0x8102
37 #define REG_CHIPID2_VALUE			0xe3
39 #define REG_DSI_LANE				0xd000
40 /* DSI lane count - 0 means 4 lanes ; 1, 2, 3 means 1, 2, 3 lanes. */
56 	regmap_reg_range(0xff, 0xff),
57 	regmap_reg_range(0x8100, 0x816b),
58 	regmap_reg_range(0x8200, 0x82aa),
59 	regmap_reg_range(0x8500, 0x85ff),
60 	regmap_reg_range(0x8600, 0x86a0),
61 	regmap_reg_range(0x8700, 0x8746),
62 	regmap_reg_range(0xd000, 0xd0a7),
63 	regmap_reg_range(0xd400, 0xd42c),
64 	regmap_reg_range(0xd800, 0xd838),
65 	regmap_reg_range(0xd9c0, 0xd9d5),
75 	.range_min = 0x0000,
76 	.range_max = 0xda00,
78 	.selector_mask = 0xff,
79 	.selector_shift = 0,
80 	.window_start = 0,
81 	.window_len = 0x100,
93 	.max_register = 0xda00,
117 	if (ret < 0) {  in lt9211_read_chipid()
123 	if (chipid[0] != REG_CHIPID0_VALUE || chipid[1] != REG_CHIPID1_VALUE ||  in lt9211_read_chipid()
125 		dev_err(ctx->dev, "Unknown Chip ID: 0x%02x 0x%02x 0x%02x\n",  in lt9211_read_chipid()
126 			chipid[0], chipid[1], chipid[2]);  in lt9211_read_chipid()
130 	return 0;  in lt9211_read_chipid()
136 		{ 0x8201, 0x18 },  in lt9211_system_init()
137 		{ 0x8606, 0x61 },  in lt9211_system_init()
138 		{ 0x8607, 0xa8 },  in lt9211_system_init()
139 		{ 0x8714, 0x08 },  in lt9211_system_init()
140 		{ 0x8715, 0x00 },  in lt9211_system_init()
141 		{ 0x8718, 0x0f },  in lt9211_system_init()
142 		{ 0x8722, 0x08 },  in lt9211_system_init()
143 		{ 0x8723, 0x00 },  in lt9211_system_init()
144 		{ 0x8726, 0x0f },  in lt9211_system_init()
145 		{ 0x810b, 0xfe },  in lt9211_system_init()
155 		{ 0x8202, 0x44 },  in lt9211_configure_rx()
156 		{ 0x8204, 0xa0 },  in lt9211_configure_rx()
157 		{ 0x8205, 0x22 },  in lt9211_configure_rx()
158 		{ 0x8207, 0x9f },  in lt9211_configure_rx()
159 		{ 0x8208, 0xfc },  in lt9211_configure_rx()
160 		/* ORR with 0xf8 here to enable DSI DN/DP swap. */  in lt9211_configure_rx()
161 		{ 0x8209, 0x01 },  in lt9211_configure_rx()
162 		{ 0x8217, 0x0c },  in lt9211_configure_rx()
163 		{ 0x8633, 0x1b },  in lt9211_configure_rx()
167 		{ 0x8120, 0x7f },  in lt9211_configure_rx()
168 		{ 0x8120, 0xff },  in lt9211_configure_rx()
172 		{ 0x8630, 0x85 },  in lt9211_configure_rx()
173 		/* 0x8588: BIT 6 set = MIPI-RX, BIT 4 unset = LVDS-TX */  in lt9211_configure_rx()
174 		{ 0x8588, 0x40 },  in lt9211_configure_rx()
175 		{ 0x85ff, 0xd0 },  in lt9211_configure_rx()
177 		{ 0xd002, 0x05 },  in lt9211_configure_rx()
181 		{ 0x810a, 0xc0 },  in lt9211_configure_rx()
182 		{ 0x8120, 0xbf },  in lt9211_configure_rx()
186 		{ 0x810a, 0xc1 },  in lt9211_configure_rx()
187 		{ 0x8120, 0xff },  in lt9211_configure_rx()
229 	ret = regmap_write(ctx->regmap, 0x8600, 0x01);  in lt9211_autodetect_rx()
237 	ret = regmap_bulk_read(ctx->regmap, 0x8608, bc, sizeof(bc));  in lt9211_autodetect_rx()
242 	byteclk = ((bc[0] & 0xf) << 16) | (bc[1] << 8) | bc[2];  in lt9211_autodetect_rx()
245 	ret = regmap_bulk_read(ctx->regmap, 0xd082, buf, sizeof(buf));  in lt9211_autodetect_rx()
249 	width = (buf[0] << 8) | buf[1];  in lt9211_autodetect_rx()
251 	format = buf[2] & 0xf;  in lt9211_autodetect_rx()
253 	if (format == 0x3) {		/* YUV422 16bit */  in lt9211_autodetect_rx()
255 	} else if (format == 0xa) {	/* RGB888 24bit */  in lt9211_autodetect_rx()
258 		dev_err(ctx->dev, "Unsupported DSI pixel format 0x%01x\n",  in lt9211_autodetect_rx()
277 	dev_dbg(ctx->dev, "RX: %dx%d format=0x%01x byteclock=%d kHz\n",  in lt9211_autodetect_rx()
280 	return 0;  in lt9211_autodetect_rx()
287 		{ 0xd00d, (mode->vtotal >> 8) & 0xff },  in lt9211_configure_timing()
288 		{ 0xd00e, mode->vtotal & 0xff },  in lt9211_configure_timing()
289 		{ 0xd00f, (mode->vdisplay >> 8) & 0xff },  in lt9211_configure_timing()
290 		{ 0xd010, mode->vdisplay & 0xff },  in lt9211_configure_timing()
291 		{ 0xd011, (mode->htotal >> 8) & 0xff },  in lt9211_configure_timing()
292 		{ 0xd012, mode->htotal & 0xff },  in lt9211_configure_timing()
293 		{ 0xd013, (mode->hdisplay >> 8) & 0xff },  in lt9211_configure_timing()
294 		{ 0xd014, mode->hdisplay & 0xff },  in lt9211_configure_timing()
295 		{ 0xd015, (mode->vsync_end - mode->vsync_start) & 0xff },  in lt9211_configure_timing()
296 		{ 0xd016, (mode->hsync_end - mode->hsync_start) & 0xff },  in lt9211_configure_timing()
297 		{ 0xd017, ((mode->vsync_start - mode->vdisplay) >> 8) & 0xff },  in lt9211_configure_timing()
298 		{ 0xd018, (mode->vsync_start - mode->vdisplay) & 0xff },  in lt9211_configure_timing()
299 		{ 0xd019, ((mode->hsync_start - mode->hdisplay) >> 8) & 0xff },  in lt9211_configure_timing()
300 		{ 0xd01a, (mode->hsync_start - mode->hdisplay) & 0xff },  in lt9211_configure_timing()
311 		{ 0xd026, 0x17 },  in lt9211_configure_plls()
312 		{ 0xd027, 0xc3 },  in lt9211_configure_plls()
313 		{ 0xd02d, 0x30 },  in lt9211_configure_plls()
314 		{ 0xd031, 0x10 },  in lt9211_configure_plls()
315 		{ 0xd023, 0x20 },  in lt9211_configure_plls()
316 		{ 0xd038, 0x02 },  in lt9211_configure_plls()
317 		{ 0xd039, 0x10 },  in lt9211_configure_plls()
318 		{ 0xd03a, 0x20 },  in lt9211_configure_plls()
319 		{ 0xd03b, 0x60 },  in lt9211_configure_plls()
320 		{ 0xd03f, 0x04 },  in lt9211_configure_plls()
321 		{ 0xd040, 0x08 },  in lt9211_configure_plls()
322 		{ 0xd041, 0x10 },  in lt9211_configure_plls()
323 		{ 0x810b, 0xee },  in lt9211_configure_plls()
324 		{ 0x810b, 0xfe },  in lt9211_configure_plls()
331 	ret = regmap_write(ctx->regmap, 0x822d, 0x48);  in lt9211_configure_plls()
336 		ret = regmap_write(ctx->regmap, 0x8235, 0x83);  in lt9211_configure_plls()
338 		ret = regmap_write(ctx->regmap, 0x8235, 0x82);  in lt9211_configure_plls()
340 		ret = regmap_write(ctx->regmap, 0x8235, 0x81);  in lt9211_configure_plls()
360 	ret = regmap_read_poll_timeout(ctx->regmap, 0xd087, pval, pval & 0x8,  in lt9211_configure_plls()
373 		{ 0x8262, 0x00 },  in lt9211_configure_tx()
375 		{ 0x823b, 0x38 | (ctx->lvds_dual_link ? BIT(7) : 0) },  in lt9211_configure_tx()
376 		{ 0x823e, 0x92 },  in lt9211_configure_tx()
377 		{ 0x823f, 0x48 },  in lt9211_configure_tx()
378 		{ 0x8240, 0x31 },  in lt9211_configure_tx()
379 		{ 0x8243, 0x80 },  in lt9211_configure_tx()
380 		{ 0x8244, 0x00 },  in lt9211_configure_tx()
381 		{ 0x8245, 0x00 },  in lt9211_configure_tx()
382 		{ 0x8249, 0x00 },  in lt9211_configure_tx()
383 		{ 0x824a, 0x01 },  in lt9211_configure_tx()
384 		{ 0x824e, 0x00 },  in lt9211_configure_tx()
385 		{ 0x824f, 0x00 },  in lt9211_configure_tx()
386 		{ 0x8250, 0x00 },  in lt9211_configure_tx()
387 		{ 0x8253, 0x00 },  in lt9211_configure_tx()
388 		{ 0x8254, 0x01 },  in lt9211_configure_tx()
389 		/* LVDS channel order, Odd:Even 0x10..A:B, 0x40..B:A */  in lt9211_configure_tx()
390 		{ 0x8646, ctx->lvds_dual_link_even_odd_swap ? 0x40 : 0x10 },  in lt9211_configure_tx()
391 		{ 0x8120, 0x7b },  in lt9211_configure_tx()
392 		{ 0x816b, 0xff },  in lt9211_configure_tx()
396 		{ 0x8559, 0x40 | (jeida ? BIT(7) : 0) |  in lt9211_configure_tx()
397 			  (de ? BIT(5) : 0) | (bpp24 ? BIT(4) : 0) },  in lt9211_configure_tx()
398 		{ 0x855a, 0xaa },  in lt9211_configure_tx()
399 		{ 0x855b, 0xaa },  in lt9211_configure_tx()
400 		{ 0x855c, ctx->lvds_dual_link ? BIT(0) : 0 },  in lt9211_configure_tx()
401 		{ 0x85a1, 0x77 },  in lt9211_configure_tx()
402 		{ 0x8640, 0x40 },  in lt9211_configure_tx()
403 		{ 0x8641, 0x34 },  in lt9211_configure_tx()
404 		{ 0x8642, 0x10 },  in lt9211_configure_tx()
405 		{ 0x8643, 0x23 },  in lt9211_configure_tx()
406 		{ 0x8644, 0x41 },  in lt9211_configure_tx()
407 		{ 0x8645, 0x02 },  in lt9211_configure_tx()
412 		{ 0x8236, 0x01 },  in lt9211_configure_tx()
413 		{ 0x8237, ctx->lvds_dual_link ? 0x2a : 0x29 },  in lt9211_configure_tx()
414 		{ 0x8238, 0x06 },  in lt9211_configure_tx()
415 		{ 0x8239, 0x30 },  in lt9211_configure_tx()
416 		{ 0x823a, 0x8e },  in lt9211_configure_tx()
417 		{ 0x8737, 0x14 },  in lt9211_configure_tx()
418 		{ 0x8713, 0x00 },  in lt9211_configure_tx()
419 		{ 0x8713, 0x80 },  in lt9211_configure_tx()
440 	ret = regmap_read_poll_timeout(ctx->regmap, 0x871f, pval, pval & 0x80,  in lt9211_configure_tx()
447 	ret = regmap_read_poll_timeout(ctx->regmap, 0x8720, pval, pval & 0x80,  in lt9211_configure_tx()
454 	return 0;  in lt9211_configure_tx()
508 …"Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n",  in lt9211_atomic_enable()
565 	gpiod_set_value(ctx->reset_gpio, 0);  in lt9211_atomic_disable()
601 	*num_input_fmts = 0;  in lt9211_atomic_get_input_bus_fmts()
609 	input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;  in lt9211_atomic_get_input_bus_fmts()
659 	ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &panel, &panel_bridge);  in lt9211_parse_dt()
660 	if (ret < 0)  in lt9211_parse_dt()
670 	return 0;  in lt9211_parse_dt()
677 		.channel = 0,  in lt9211_host_attach()
688 	endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);  in lt9211_host_attach()
698 	if (dsi_lanes < 0)  in lt9211_host_attach()
716 	if (ret < 0) {  in lt9211_host_attach()
721 	return 0;  in lt9211_host_attach()