Lines Matching +full:0 +full:xd800
33 #define CAYMAN_MAX_BACKENDS_MASK 0xFF
34 #define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF
36 #define CAYMAN_MAX_SIMDS_MASK 0xFFFF
37 #define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF
39 #define CAYMAN_MAX_PIPES_MASK 0xFF
40 #define CAYMAN_MAX_LDS_NUM 0xFFFF
42 #define CAYMAN_MAX_TCC_MASK 0xFF
44 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
45 #define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001
47 #define DMIF_ADDR_CONFIG 0xBD4
50 #define CG_ECLK_CNTL 0x620
51 # define ECLK_DIVIDER_MASK 0x7f
53 #define CG_ECLK_STATUS 0x624
54 # define ECLK_STATUS (1 << 0)
57 #define DMIF_ADDR_CALC 0xC00
59 #define SRBM_GFX_CNTL 0x0E44
60 #define RINGID(x) (((x) & 0x3) << 0)
61 #define VMID(x) (((x) & 0x7) << 0)
62 #define SRBM_STATUS 0x0E50
74 #define SRBM_SOFT_RESET 0x0E60
92 #define SRBM_READ_ERROR 0xE98
93 #define SRBM_INT_CNTL 0xEA0
94 #define SRBM_INT_ACK 0xEA8
96 #define SRBM_STATUS2 0x0EC4
100 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
101 #define REQUEST_TYPE(x) (((x) & 0xf) << 0)
102 #define RESPONSE_TYPE_MASK 0x000000F0
104 #define VM_L2_CNTL 0x1400
105 #define ENABLE_L2_CACHE (1 << 0)
112 * 0 physical = logical
117 #define VM_L2_CNTL2 0x1404
118 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
120 #define VM_L2_CNTL3 0x1408
121 #define BANK_SELECT(x) ((x) << 0)
125 #define VM_L2_STATUS 0x140C
126 #define L2_BUSY (1 << 0)
127 #define VM_CONTEXT0_CNTL 0x1410
128 #define ENABLE_CONTEXT (1 << 0)
142 #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24)
143 #define VM_CONTEXT1_CNTL 0x1414
144 #define VM_CONTEXT0_CNTL2 0x1430
145 #define VM_CONTEXT1_CNTL2 0x1434
146 #define VM_INVALIDATE_REQUEST 0x1478
147 #define VM_INVALIDATE_RESPONSE 0x147c
148 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
149 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
150 #define PROTECTIONS_MASK (0xf << 0)
151 #define PROTECTIONS_SHIFT 0
152 /* bit 0: range
158 #define MEMORY_CLIENT_ID_MASK (0xff << 12)
162 #define FAULT_VMID_MASK (0x7 << 25)
164 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
165 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
166 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
167 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
168 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
170 #define MC_SHARED_CHMAP 0x2004
172 #define NOOFCHAN_MASK 0x00003000
173 #define MC_SHARED_CHREMAP 0x2008
175 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
176 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
177 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
178 #define MC_VM_MX_L1_TLB_CNTL 0x2064
179 #define ENABLE_L1_TLB (1 << 0)
181 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
185 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
187 #define FUS_MC_VM_FB_OFFSET 0x2068
189 #define MC_SHARED_BLACKOUT_CNTL 0x20ac
190 #define MC_ARB_RAMCFG 0x2760
191 #define NOOFBANK_SHIFT 0
192 #define NOOFBANK_MASK 0x00000003
194 #define NOOFRANK_MASK 0x00000004
196 #define NOOFROWS_MASK 0x00000038
198 #define NOOFCOLS_MASK 0x000000C0
200 #define CHANSIZE_MASK 0x00000100
202 #define BURSTLENGTH_MASK 0x00000200
204 #define MC_SEQ_SUP_CNTL 0x28c8
205 #define RUN_MASK (1 << 0)
206 #define MC_SEQ_SUP_PGM 0x28cc
207 #define MC_IO_PAD_CNTL_D0 0x29d0
209 #define MC_SEQ_MISC0 0x2a00
211 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
213 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44
214 #define MC_SEQ_IO_DEBUG_DATA 0x2a48
216 #define HDP_HOST_PATH_CNTL 0x2C00
217 #define HDP_NONSURFACE_BASE 0x2C04
218 #define HDP_NONSURFACE_INFO 0x2C08
219 #define HDP_NONSURFACE_SIZE 0x2C0C
220 #define HDP_ADDR_CONFIG 0x2F48
221 #define HDP_MISC_CNTL 0x2F4C
222 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
224 #define CC_SYS_RB_BACKEND_DISABLE 0x3F88
225 #define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C
226 #define CGTS_SYS_TCC_DISABLE 0x3F90
227 #define CGTS_USER_SYS_TCC_DISABLE 0x3F94
229 #define RLC_GFX_INDEX 0x3FC4
231 #define CONFIG_MEMSIZE 0x5428
233 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
234 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
236 #define GRBM_CNTL 0x8000
237 #define GRBM_READ_TIMEOUT(x) ((x) << 0)
238 #define GRBM_STATUS 0x8010
239 #define CMDFIFO_AVAIL_MASK 0x0000000F
266 #define GRBM_STATUS_SE0 0x8014
267 #define GRBM_STATUS_SE1 0x8018
268 #define SE_SX_CLEAN (1 << 0)
280 #define GRBM_SOFT_RESET 0x8020
281 #define SOFT_RESET_CP (1 << 0)
295 #define GRBM_GFX_INDEX 0x802C
296 #define INSTANCE_INDEX(x) ((x) << 0)
301 #define SCRATCH_REG0 0x8500
302 #define SCRATCH_REG1 0x8504
303 #define SCRATCH_REG2 0x8508
304 #define SCRATCH_REG3 0x850C
305 #define SCRATCH_REG4 0x8510
306 #define SCRATCH_REG5 0x8514
307 #define SCRATCH_REG6 0x8518
308 #define SCRATCH_REG7 0x851C
309 #define SCRATCH_UMSK 0x8540
310 #define SCRATCH_ADDR 0x8544
311 #define CP_SEM_WAIT_TIMER 0x85BC
312 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
313 #define CP_COHER_CNTL2 0x85E8
314 #define CP_STALLED_STAT1 0x8674
315 #define CP_STALLED_STAT2 0x8678
316 #define CP_BUSY_STAT 0x867C
317 #define CP_STAT 0x8680
318 #define CP_ME_CNTL 0x86D8
321 #define CP_RB2_RPTR 0x86f8
322 #define CP_RB1_RPTR 0x86fc
323 #define CP_RB0_RPTR 0x8700
324 #define CP_RB_WPTR_DELAY 0x8704
325 #define CP_MEQ_THRESHOLDS 0x8764
326 #define MEQ1_START(x) ((x) << 0)
328 #define CP_PERFMON_CNTL 0x87FC
330 #define VGT_CACHE_INVALIDATION 0x88C4
331 #define CACHE_INVALIDATION(x) ((x) << 0)
332 #define VC_ONLY 0
336 #define NO_AUTO 0
340 #define VGT_GS_VERTEX_REUSE 0x88D4
342 #define CC_GC_SHADER_PIPE_CONFIG 0x8950
343 #define GC_USER_SHADER_PIPE_CONFIG 0x8954
345 #define INACTIVE_QD_PIPES_MASK 0x0000FF00
348 #define INACTIVE_SIMDS_MASK 0xFFFF0000
351 #define VGT_PRIMITIVE_TYPE 0x8958
352 #define VGT_NUM_INSTANCES 0x8974
353 #define VGT_TF_RING_SIZE 0x8988
354 #define VGT_OFFCHIP_LDS_BASE 0x89b4
356 #define PA_SC_LINE_STIPPLE_STATE 0x8B10
357 #define PA_CL_ENHANCE 0x8A14
358 #define CLIP_VTX_REORDER_ENA (1 << 0)
360 #define PA_SC_FIFO_SIZE 0x8BCC
361 #define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
364 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
365 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
368 #define SQ_CONFIG 0x8C00
369 #define VC_ENABLE (1 << 0)
374 #define SQ_GPR_RESOURCE_MGMT_1 0x8C04
375 #define NUM_PS_GPRS(x) ((x) << 0)
378 #define SQ_ESGS_RING_SIZE 0x8c44
379 #define SQ_GSVS_RING_SIZE 0x8c4c
380 #define SQ_ESTMP_RING_BASE 0x8c50
381 #define SQ_ESTMP_RING_SIZE 0x8c54
382 #define SQ_GSTMP_RING_BASE 0x8c58
383 #define SQ_GSTMP_RING_SIZE 0x8c5c
384 #define SQ_VSTMP_RING_BASE 0x8c60
385 #define SQ_VSTMP_RING_SIZE 0x8c64
386 #define SQ_PSTMP_RING_BASE 0x8c68
387 #define SQ_PSTMP_RING_SIZE 0x8c6c
388 #define SQ_MS_FIFO_SIZES 0x8CF0
389 #define CACHE_FIFO_SIZE(x) ((x) << 0)
393 #define SQ_LSTMP_RING_BASE 0x8e10
394 #define SQ_LSTMP_RING_SIZE 0x8e14
395 #define SQ_HSTMP_RING_BASE 0x8e18
396 #define SQ_HSTMP_RING_SIZE 0x8e1c
397 #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C
399 #define SQ_CONST_MEM_BASE 0x8df8
401 #define SX_EXPORT_BUFFER_SIZES 0x900C
402 #define COLOR_BUFFER_SIZE(x) ((x) << 0)
405 #define SX_DEBUG_1 0x9058
408 #define SPI_CONFIG_CNTL 0x9100
409 #define GPR_WRITE_PRIORITY(x) ((x) << 0)
410 #define SPI_CONFIG_CNTL_1 0x913C
411 #define VTX_DONE_DELAY(x) ((x) << 0)
415 #define CGTS_TCC_DISABLE 0x9148
416 #define CGTS_USER_TCC_DISABLE 0x914C
417 #define TCC_DISABLE_MASK 0xFFFF0000
419 #define CGTS_SM_CTRL_REG 0x9150
422 #define TA_CNTL_AUX 0x9508
423 #define DISABLE_CUBE_WRAP (1 << 0)
426 #define TCP_CHAN_STEER_LO 0x960c
427 #define TCP_CHAN_STEER_HI 0x9610
429 #define CC_RB_BACKEND_DISABLE 0x98F4
431 #define GB_ADDR_CONFIG 0x98F8
432 #define NUM_PIPES(x) ((x) << 0)
433 #define NUM_PIPES_MASK 0x00000007
434 #define NUM_PIPES_SHIFT 0
436 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
440 #define NUM_SHADER_ENGINES_MASK 0x00003000
443 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
446 #define NUM_GPUS_MASK 0x00700000
449 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000
452 #define ROW_SIZE_MASK 0x30000000
455 #define NUM_LOWER_PIPES_MASK 0x40000000
457 #define GB_BACKEND_MAP 0x98FC
459 #define CB_PERF_CTR0_SEL_0 0x9A20
460 #define CB_PERF_CTR0_SEL_1 0x9A24
461 #define CB_PERF_CTR1_SEL_0 0x9A28
462 #define CB_PERF_CTR1_SEL_1 0x9A2C
463 #define CB_PERF_CTR2_SEL_0 0x9A30
464 #define CB_PERF_CTR2_SEL_1 0x9A34
465 #define CB_PERF_CTR3_SEL_0 0x9A38
466 #define CB_PERF_CTR3_SEL_1 0x9A3C
468 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C
469 #define BACKEND_DISABLE_MASK 0x00FF0000
472 #define SMX_DC_CTL0 0xA020
473 #define USE_HASH_FUNCTION (1 << 0)
477 #define SMX_EVENT_CTL 0xA02C
478 #define ES_FLUSH_CTL(x) ((x) << 0)
483 #define CP_RB0_BASE 0xC100
484 #define CP_RB0_CNTL 0xC104
485 #define RB_BUFSZ(x) ((x) << 0)
490 #define CP_RB0_RPTR_ADDR 0xC10C
491 #define CP_RB0_RPTR_ADDR_HI 0xC110
492 #define CP_RB0_WPTR 0xC114
494 #define CP_INT_CNTL 0xC124
499 #define CP_RB1_BASE 0xC180
500 #define CP_RB1_CNTL 0xC184
501 #define CP_RB1_RPTR_ADDR 0xC188
502 #define CP_RB1_RPTR_ADDR_HI 0xC18C
503 #define CP_RB1_WPTR 0xC190
504 #define CP_RB2_BASE 0xC194
505 #define CP_RB2_CNTL 0xC198
506 #define CP_RB2_RPTR_ADDR 0xC19C
507 #define CP_RB2_RPTR_ADDR_HI 0xC1A0
508 #define CP_RB2_WPTR 0xC1A4
509 #define CP_PFP_UCODE_ADDR 0xC150
510 #define CP_PFP_UCODE_DATA 0xC154
511 #define CP_ME_RAM_RADDR 0xC158
512 #define CP_ME_RAM_WADDR 0xC15C
513 #define CP_ME_RAM_DATA 0xC160
514 #define CP_DEBUG 0xC1FC
516 #define VGT_EVENT_INITIATOR 0x28a90
517 # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0)
518 # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
521 #define TN_CURRENT_GNB_TEMP 0x1F390
524 #define SMC_MSG 0x20c
525 #define HOST_SMC_MSG(x) ((x) << 0)
526 #define HOST_SMC_MSG_MASK (0xff << 0)
527 #define HOST_SMC_MSG_SHIFT 0
529 #define HOST_SMC_RESP_MASK (0xff << 8)
532 #define SMC_HOST_MSG_MASK (0xff << 16)
535 #define SMC_HOST_RESP_MASK (0xff << 24)
538 #define CG_SPLL_FUNC_CNTL 0x600
539 #define SPLL_RESET (1 << 0)
543 #define SPLL_REF_DIV_MASK (0x3f << 4)
545 #define SPLL_PDIV_A_MASK (0x7f << 20)
547 #define CG_SPLL_FUNC_CNTL_2 0x604
548 #define SCLK_MUX_SEL(x) ((x) << 0)
549 #define SCLK_MUX_SEL_MASK (0x1ff << 0)
550 #define CG_SPLL_FUNC_CNTL_3 0x608
551 #define SPLL_FB_DIV(x) ((x) << 0)
552 #define SPLL_FB_DIV_MASK (0x3ffffff << 0)
553 #define SPLL_FB_DIV_SHIFT 0
556 #define MPLL_CNTL_MODE 0x61c
560 #define MPLL_AD_FUNC_CNTL 0x624
561 #define CLKF(x) ((x) << 0)
562 #define CLKF_MASK (0x7f << 0)
564 #define CLKR_MASK (0x1f << 7)
566 #define CLKFRAC_MASK (0x1f << 12)
570 #define IBIAS_MASK (0x3ff << 20)
573 #define MPLL_AD_FUNC_CNTL_2 0x628
578 #define MPLL_DQ_FUNC_CNTL 0x62c
579 #define MPLL_DQ_FUNC_CNTL_2 0x630
581 #define GENERAL_PWRMGT 0x63c
582 # define GLOBAL_PWRMGT_EN (1 << 0)
599 #define SCLK_PWRMGT_CNTL 0x644
600 # define SCLK_PWRMGT_OFF (1 << 0)
613 #define MCLK_PWRMGT_CNTL 0x648
614 # define DLL_SPEED(x) ((x) << 0)
615 # define DLL_SPEED_MASK (0x1f << 0)
639 #define DLL_CNTL 0x64c
649 #define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c
650 # define CURRENT_STATE_INDEX_MASK (0xf << 4)
653 #define CG_AT 0x6d4
654 # define CG_R(x) ((x) << 0)
655 # define CG_R_MASK (0xffff << 0)
657 # define CG_L_MASK (0xffff << 16)
659 #define CG_BIF_REQ_AND_RSP 0x7f4
660 #define CG_CLIENT_REQ(x) ((x) << 0)
661 #define CG_CLIENT_REQ_MASK (0xff << 0)
662 #define CG_CLIENT_REQ_SHIFT 0
664 #define CG_CLIENT_RESP_MASK (0xff << 8)
667 #define CLIENT_CG_REQ_MASK (0xff << 16)
670 #define CLIENT_CG_RESP_MASK (0xff << 24)
673 #define CG_SPLL_SPREAD_SPECTRUM 0x790
674 #define SSEN (1 << 0)
676 #define CLK_S_MASK (0xfff << 4)
678 #define CG_SPLL_SPREAD_SPECTRUM_2 0x794
679 #define CLK_V(x) ((x) << 0)
680 #define CLK_V_MASK (0x3ffffff << 0)
681 #define CLK_V_SHIFT 0
683 #define SMC_SCRATCH0 0x81c
685 #define CG_SPLL_FUNC_CNTL_4 0x850
687 #define MPLL_SS1 0x85c
688 #define CLKV(x) ((x) << 0)
689 #define CLKV_MASK (0x3ffffff << 0)
690 #define MPLL_SS2 0x860
691 #define CLKS(x) ((x) << 0)
692 #define CLKS_MASK (0xfff << 0)
694 #define CG_CAC_CTRL 0x88c
695 #define TID_CNT(x) ((x) << 0)
696 #define TID_CNT_MASK (0x3fff << 0)
698 #define TID_UNIT_MASK (0xf << 14)
700 #define CG_IND_ADDR 0x8f8
701 #define CG_IND_DATA 0x8fc
703 #define CG_CGTT_LOCAL_0 0x00
704 #define CG_CGTT_LOCAL_1 0x01
706 #define MC_CG_CONFIG 0x25bc
707 #define MCDW_WR_ENABLE (1 << 0)
714 #define INDEX_MASK (0xfff << 6)
717 #define MC_ARB_CAC_CNTL 0x2750
718 #define ENABLE (1 << 0)
720 #define READ_WEIGHT_MASK (0x3f << 1)
723 #define WRITE_WEIGHT_MASK (0x3f << 7)
727 #define MC_ARB_DRAM_TIMING 0x2774
728 #define MC_ARB_DRAM_TIMING2 0x2778
730 #define MC_ARB_RFSH_RATE 0x27b0
731 #define POWERMODE0(x) ((x) << 0)
732 #define POWERMODE0_MASK (0xff << 0)
733 #define POWERMODE0_SHIFT 0
735 #define POWERMODE1_MASK (0xff << 8)
738 #define POWERMODE2_MASK (0xff << 16)
741 #define POWERMODE3_MASK (0xff << 24)
744 #define MC_ARB_CG 0x27e8
745 #define CG_ARB_REQ(x) ((x) << 0)
746 #define CG_ARB_REQ_MASK (0xff << 0)
747 #define CG_ARB_REQ_SHIFT 0
749 #define CG_ARB_RESP_MASK (0xff << 8)
752 #define ARB_CG_REQ_MASK (0xff << 16)
755 #define ARB_CG_RESP_MASK (0xff << 24)
758 #define MC_ARB_DRAM_TIMING_1 0x27f0
759 #define MC_ARB_DRAM_TIMING_2 0x27f4
760 #define MC_ARB_DRAM_TIMING_3 0x27f8
761 #define MC_ARB_DRAM_TIMING2_1 0x27fc
762 #define MC_ARB_DRAM_TIMING2_2 0x2800
763 #define MC_ARB_DRAM_TIMING2_3 0x2804
764 #define MC_ARB_BURST_TIME 0x2808
765 #define STATE0(x) ((x) << 0)
766 #define STATE0_MASK (0x1f << 0)
767 #define STATE0_SHIFT 0
769 #define STATE1_MASK (0x1f << 5)
772 #define STATE2_MASK (0x1f << 10)
775 #define STATE3_MASK (0x1f << 15)
778 #define MC_CG_DATAPORT 0x2884
780 #define MC_SEQ_RAS_TIMING 0x28a0
781 #define MC_SEQ_CAS_TIMING 0x28a4
782 #define MC_SEQ_MISC_TIMING 0x28a8
783 #define MC_SEQ_MISC_TIMING2 0x28ac
784 #define MC_SEQ_PMG_TIMING 0x28b0
785 #define MC_SEQ_RD_CTL_D0 0x28b4
786 #define MC_SEQ_RD_CTL_D1 0x28b8
787 #define MC_SEQ_WR_CTL_D0 0x28bc
788 #define MC_SEQ_WR_CTL_D1 0x28c0
790 #define MC_SEQ_MISC0 0x2a00
792 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
794 #define MC_SEQ_MISC1 0x2a04
795 #define MC_SEQ_RESERVE_M 0x2a08
796 #define MC_PMG_CMD_EMRS 0x2a0c
798 #define MC_SEQ_MISC3 0x2a2c
800 #define MC_SEQ_MISC5 0x2a54
801 #define MC_SEQ_MISC6 0x2a58
803 #define MC_SEQ_MISC7 0x2a64
805 #define MC_SEQ_RAS_TIMING_LP 0x2a6c
806 #define MC_SEQ_CAS_TIMING_LP 0x2a70
807 #define MC_SEQ_MISC_TIMING_LP 0x2a74
808 #define MC_SEQ_MISC_TIMING2_LP 0x2a78
809 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c
810 #define MC_SEQ_WR_CTL_D1_LP 0x2a80
811 #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84
812 #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88
814 #define MC_PMG_CMD_MRS 0x2aac
816 #define MC_SEQ_RD_CTL_D0_LP 0x2b1c
817 #define MC_SEQ_RD_CTL_D1_LP 0x2b20
819 #define MC_PMG_CMD_MRS1 0x2b44
820 #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48
821 #define MC_SEQ_PMG_TIMING_LP 0x2b4c
823 #define MC_PMG_CMD_MRS2 0x2b5c
824 #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60
826 #define AUX_CONTROL 0x6200
827 #define AUX_EN (1 << 0)
829 #define AUX_LS_UPDATE_DISABLE(x) (((x) & 0x1) << 12)
830 #define AUX_HPD_DISCON(x) (((x) & 0x1) << 16)
832 #define AUX_HPD_SEL(x) (((x) & 0x7) << 20)
836 #define AUX_SW_CONTROL 0x6204
837 #define AUX_SW_GO (1 << 0)
839 #define AUX_SW_START_DELAY(x) (((x) & 0xf) << 4)
840 #define AUX_SW_WR_BYTES(x) (((x) & 0x1f) << 16)
842 #define AUX_SW_INTERRUPT_CONTROL 0x620c
843 #define AUX_SW_DONE_INT (1 << 0)
848 #define AUX_SW_STATUS 0x6210
849 #define AUX_SW_DONE (1 << 0)
851 #define AUX_SW_RX_TIMEOUT_STATE(x) (((x) & 0x7) << 4)
866 #define AUX_SW_DATA 0x6218
867 #define AUX_SW_DATA_RW (1 << 0)
868 #define AUX_SW_DATA_MASK(x) (((x) & 0xff) << 8)
869 #define AUX_SW_DATA_INDEX(x) (((x) & 0x1f) << 16)
872 #define LB_SYNC_RESET_SEL 0x6b28
873 #define LB_SYNC_RESET_SEL_MASK (3 << 0)
874 #define LB_SYNC_RESET_SEL_SHIFT 0
876 #define DC_STUTTER_CNTL 0x6b30
877 #define DC_STUTTER_ENABLE_A (1 << 0)
880 #define SQ_CAC_THRESHOLD 0x8e4c
881 #define VSP(x) ((x) << 0)
882 #define VSP_MASK (0xff << 0)
883 #define VSP_SHIFT 0
885 #define VSP0_MASK (0xff << 8)
888 #define GPR_MASK (0xff << 16)
891 #define SQ_POWER_THROTTLE 0x8e58
892 #define MIN_POWER(x) ((x) << 0)
893 #define MIN_POWER_MASK (0x3fff << 0)
894 #define MIN_POWER_SHIFT 0
896 #define MAX_POWER_MASK (0x3fff << 16)
897 #define MAX_POWER_SHIFT 0
898 #define SQ_POWER_THROTTLE2 0x8e5c
899 #define MAX_POWER_DELTA(x) ((x) << 0)
900 #define MAX_POWER_DELTA_MASK (0x3fff << 0)
901 #define MAX_POWER_DELTA_SHIFT 0
903 #define STI_SIZE_MASK (0x3ff << 16)
906 #define LTI_RATIO_MASK (0xf << 27)
910 #define CG_CAC_REGION_1_WEIGHT_0 0x83
911 #define WEIGHT_TCP_SIG0(x) ((x) << 0)
912 #define WEIGHT_TCP_SIG0_MASK (0x3f << 0)
913 #define WEIGHT_TCP_SIG0_SHIFT 0
915 #define WEIGHT_TCP_SIG1_MASK (0x3f << 6)
918 #define WEIGHT_TA_SIG_MASK (0x3f << 12)
920 #define CG_CAC_REGION_1_WEIGHT_1 0x84
921 #define WEIGHT_TCC_EN0(x) ((x) << 0)
922 #define WEIGHT_TCC_EN0_MASK (0x3f << 0)
923 #define WEIGHT_TCC_EN0_SHIFT 0
925 #define WEIGHT_TCC_EN1_MASK (0x3f << 6)
928 #define WEIGHT_TCC_EN2_MASK (0x3f << 12)
931 #define WEIGHT_TCC_EN3_MASK (0x3f << 18)
933 #define CG_CAC_REGION_2_WEIGHT_0 0x85
934 #define WEIGHT_CB_EN0(x) ((x) << 0)
935 #define WEIGHT_CB_EN0_MASK (0x3f << 0)
936 #define WEIGHT_CB_EN0_SHIFT 0
938 #define WEIGHT_CB_EN1_MASK (0x3f << 6)
941 #define WEIGHT_CB_EN2_MASK (0x3f << 12)
944 #define WEIGHT_CB_EN3_MASK (0x3f << 18)
946 #define CG_CAC_REGION_2_WEIGHT_1 0x86
947 #define WEIGHT_DB_SIG0(x) ((x) << 0)
948 #define WEIGHT_DB_SIG0_MASK (0x3f << 0)
949 #define WEIGHT_DB_SIG0_SHIFT 0
951 #define WEIGHT_DB_SIG1_MASK (0x3f << 6)
954 #define WEIGHT_DB_SIG2_MASK (0x3f << 12)
957 #define WEIGHT_DB_SIG3_MASK (0x3f << 18)
959 #define CG_CAC_REGION_2_WEIGHT_2 0x87
960 #define WEIGHT_SXM_SIG0(x) ((x) << 0)
961 #define WEIGHT_SXM_SIG0_MASK (0x3f << 0)
962 #define WEIGHT_SXM_SIG0_SHIFT 0
964 #define WEIGHT_SXM_SIG1_MASK (0x3f << 6)
967 #define WEIGHT_SXM_SIG2_MASK (0x3f << 12)
970 #define WEIGHT_SXS_SIG0_MASK (0x3f << 18)
973 #define WEIGHT_SXS_SIG1_MASK (0x3f << 24)
975 #define CG_CAC_REGION_3_WEIGHT_0 0x88
976 #define WEIGHT_XBR_0(x) ((x) << 0)
977 #define WEIGHT_XBR_0_MASK (0x3f << 0)
978 #define WEIGHT_XBR_0_SHIFT 0
980 #define WEIGHT_XBR_1_MASK (0x3f << 6)
983 #define WEIGHT_XBR_2_MASK (0x3f << 12)
986 #define WEIGHT_SPI_SIG0_MASK (0x3f << 18)
988 #define CG_CAC_REGION_3_WEIGHT_1 0x89
989 #define WEIGHT_SPI_SIG1(x) ((x) << 0)
990 #define WEIGHT_SPI_SIG1_MASK (0x3f << 0)
991 #define WEIGHT_SPI_SIG1_SHIFT 0
993 #define WEIGHT_SPI_SIG2_MASK (0x3f << 6)
996 #define WEIGHT_SPI_SIG3_MASK (0x3f << 12)
999 #define WEIGHT_SPI_SIG4_MASK (0x3f << 18)
1002 #define WEIGHT_SPI_SIG5_MASK (0x3f << 24)
1004 #define CG_CAC_REGION_4_WEIGHT_0 0x8a
1005 #define WEIGHT_LDS_SIG0(x) ((x) << 0)
1006 #define WEIGHT_LDS_SIG0_MASK (0x3f << 0)
1007 #define WEIGHT_LDS_SIG0_SHIFT 0
1009 #define WEIGHT_LDS_SIG1_MASK (0x3f << 6)
1012 #define WEIGHT_SC_MASK (0x3f << 24)
1014 #define CG_CAC_REGION_4_WEIGHT_1 0x8b
1015 #define WEIGHT_BIF(x) ((x) << 0)
1016 #define WEIGHT_BIF_MASK (0x3f << 0)
1017 #define WEIGHT_BIF_SHIFT 0
1019 #define WEIGHT_CP_MASK (0x3f << 6)
1022 #define WEIGHT_PA_SIG0_MASK (0x3f << 12)
1025 #define WEIGHT_PA_SIG1_MASK (0x3f << 18)
1028 #define WEIGHT_VGT_SIG0_MASK (0x3f << 24)
1030 #define CG_CAC_REGION_4_WEIGHT_2 0x8c
1031 #define WEIGHT_VGT_SIG1(x) ((x) << 0)
1032 #define WEIGHT_VGT_SIG1_MASK (0x3f << 0)
1033 #define WEIGHT_VGT_SIG1_SHIFT 0
1035 #define WEIGHT_VGT_SIG2_MASK (0x3f << 6)
1038 #define WEIGHT_DC_SIG0_MASK (0x3f << 12)
1041 #define WEIGHT_DC_SIG1_MASK (0x3f << 18)
1044 #define WEIGHT_DC_SIG2_MASK (0x3f << 24)
1046 #define CG_CAC_REGION_4_WEIGHT_3 0x8d
1047 #define WEIGHT_DC_SIG3(x) ((x) << 0)
1048 #define WEIGHT_DC_SIG3_MASK (0x3f << 0)
1049 #define WEIGHT_DC_SIG3_SHIFT 0
1051 #define WEIGHT_UVD_SIG0_MASK (0x3f << 6)
1054 #define WEIGHT_UVD_SIG1_MASK (0x3f << 12)
1057 #define WEIGHT_SPARE0_MASK (0x3f << 18)
1060 #define WEIGHT_SPARE1_MASK (0x3f << 24)
1062 #define CG_CAC_REGION_5_WEIGHT_0 0x8e
1063 #define WEIGHT_SQ_VSP(x) ((x) << 0)
1064 #define WEIGHT_SQ_VSP_MASK (0x3fff << 0)
1065 #define WEIGHT_SQ_VSP_SHIFT 0
1067 #define WEIGHT_SQ_VSP0_MASK (0x3fff << 14)
1069 #define CG_CAC_REGION_4_OVERRIDE_4 0xab
1071 #define OVR_MODE_SPARE_0_MASK (0x1 << 16)
1074 #define OVR_VAL_SPARE_0_MASK (0x1 << 17)
1077 #define OVR_MODE_SPARE_1_MASK (0x3f << 18)
1080 #define OVR_VAL_SPARE_1_MASK (0x3f << 19)
1082 #define CG_CAC_REGION_5_WEIGHT_1 0xb7
1083 #define WEIGHT_SQ_GPR(x) ((x) << 0)
1084 #define WEIGHT_SQ_GPR_MASK (0x3fff << 0)
1085 #define WEIGHT_SQ_GPR_SHIFT 0
1087 #define WEIGHT_SQ_LDS_MASK (0x3fff << 14)
1091 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
1092 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
1093 # define LC_LINK_WIDTH_SHIFT 0
1094 # define LC_LINK_WIDTH_MASK 0x7
1095 # define LC_LINK_WIDTH_X0 0
1102 # define LC_LINK_WIDTH_RD_MASK 0x70
1110 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
1111 # define LC_GEN2_EN_STRAP (1 << 0)
1115 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
1121 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
1125 #define MM_CFGREGS_CNTL 0x544c
1127 #define LINK_CNTL2 0x88 /* F0 */
1128 # define TARGET_LINK_SPEED_MASK (0xf << 0)
1134 #define UVD_SEMA_ADDR_LOW 0xEF00
1135 #define UVD_SEMA_ADDR_HIGH 0xEF04
1136 #define UVD_SEMA_CMD 0xEF08
1137 #define UVD_UDEC_ADDR_CONFIG 0xEF4C
1138 #define UVD_UDEC_DB_ADDR_CONFIG 0xEF50
1139 #define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54
1140 #define UVD_NO_OP 0xEFFC
1141 #define UVD_RBC_RB_RPTR 0xF690
1142 #define UVD_RBC_RB_WPTR 0xF694
1143 #define UVD_STATUS 0xf6bc
1149 (((reg) >> 2) & 0xFFFF) | \
1150 ((n) & 0x3FFF) << 16)
1151 #define CP_PACKET2 0x80000000
1152 #define PACKET2_PAD_SHIFT 0
1153 #define PACKET2_PAD_MASK (0x3fffffff << 0)
1158 (((op) & 0xFF) << 8) | \
1159 ((n) & 0x3FFF) << 16)
1162 #define PACKET3_NOP 0x10
1163 #define PACKET3_SET_BASE 0x11
1164 #define PACKET3_CLEAR_STATE 0x12
1165 #define PACKET3_INDEX_BUFFER_SIZE 0x13
1166 #define PACKET3_DEALLOC_STATE 0x14
1167 #define PACKET3_DISPATCH_DIRECT 0x15
1168 #define PACKET3_DISPATCH_INDIRECT 0x16
1169 #define PACKET3_INDIRECT_BUFFER_END 0x17
1170 #define PACKET3_MODE_CONTROL 0x18
1171 #define PACKET3_SET_PREDICATION 0x20
1172 #define PACKET3_REG_RMW 0x21
1173 #define PACKET3_COND_EXEC 0x22
1174 #define PACKET3_PRED_EXEC 0x23
1175 #define PACKET3_DRAW_INDIRECT 0x24
1176 #define PACKET3_DRAW_INDEX_INDIRECT 0x25
1177 #define PACKET3_INDEX_BASE 0x26
1178 #define PACKET3_DRAW_INDEX_2 0x27
1179 #define PACKET3_CONTEXT_CONTROL 0x28
1180 #define PACKET3_DRAW_INDEX_OFFSET 0x29
1181 #define PACKET3_INDEX_TYPE 0x2A
1182 #define PACKET3_DRAW_INDEX 0x2B
1183 #define PACKET3_DRAW_INDEX_AUTO 0x2D
1184 #define PACKET3_DRAW_INDEX_IMMD 0x2E
1185 #define PACKET3_NUM_INSTANCES 0x2F
1186 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
1187 #define PACKET3_INDIRECT_BUFFER 0x32
1188 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
1189 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
1190 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
1191 #define PACKET3_WRITE_DATA 0x37
1192 #define PACKET3_MEM_SEMAPHORE 0x39
1193 #define PACKET3_MPEG_INDEX 0x3A
1194 #define PACKET3_WAIT_REG_MEM 0x3C
1195 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
1196 /* 0 - always
1205 /* 0 - reg
1209 /* 0 - me
1212 #define PACKET3_MEM_WRITE 0x3D
1213 #define PACKET3_PFP_SYNC_ME 0x42
1214 #define PACKET3_SURFACE_SYNC 0x43
1235 #define PACKET3_ME_INITIALIZE 0x44
1237 #define PACKET3_COND_WRITE 0x45
1238 #define PACKET3_EVENT_WRITE 0x46
1239 #define EVENT_TYPE(x) ((x) << 0)
1241 /* 0 - any non-TS event
1248 #define PACKET3_EVENT_WRITE_EOP 0x47
1250 /* 0 - discard
1256 /* 0 - none
1257 * 1 - interrupt only (DATA_SEL = 0)
1260 #define PACKET3_EVENT_WRITE_EOS 0x48
1261 #define PACKET3_PREAMBLE_CNTL 0x4A
1264 #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C
1265 #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D
1266 #define PACKET3_ALU_PS_CONST_UPDATE 0x4E
1267 #define PACKET3_ALU_VS_CONST_UPDATE 0x4F
1268 #define PACKET3_ONE_REG_WRITE 0x57
1269 #define PACKET3_SET_CONFIG_REG 0x68
1270 #define PACKET3_SET_CONFIG_REG_START 0x00008000
1271 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00
1272 #define PACKET3_SET_CONTEXT_REG 0x69
1273 #define PACKET3_SET_CONTEXT_REG_START 0x00028000
1274 #define PACKET3_SET_CONTEXT_REG_END 0x00029000
1275 #define PACKET3_SET_ALU_CONST 0x6A
1277 #define PACKET3_SET_BOOL_CONST 0x6B
1278 #define PACKET3_SET_BOOL_CONST_START 0x0003a500
1279 #define PACKET3_SET_BOOL_CONST_END 0x0003a518
1280 #define PACKET3_SET_LOOP_CONST 0x6C
1281 #define PACKET3_SET_LOOP_CONST_START 0x0003a200
1282 #define PACKET3_SET_LOOP_CONST_END 0x0003a500
1283 #define PACKET3_SET_RESOURCE 0x6D
1284 #define PACKET3_SET_RESOURCE_START 0x00030000
1285 #define PACKET3_SET_RESOURCE_END 0x00038000
1286 #define PACKET3_SET_SAMPLER 0x6E
1287 #define PACKET3_SET_SAMPLER_START 0x0003c000
1288 #define PACKET3_SET_SAMPLER_END 0x0003c600
1289 #define PACKET3_SET_CTL_CONST 0x6F
1290 #define PACKET3_SET_CTL_CONST_START 0x0003cff0
1291 #define PACKET3_SET_CTL_CONST_END 0x0003ff0c
1292 #define PACKET3_SET_RESOURCE_OFFSET 0x70
1293 #define PACKET3_SET_ALU_CONST_VS 0x71
1294 #define PACKET3_SET_ALU_CONST_DI 0x72
1295 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
1296 #define PACKET3_SET_RESOURCE_INDIRECT 0x74
1297 #define PACKET3_SET_APPEND_CNT 0x75
1298 #define PACKET3_ME_WRITE 0x7A
1300 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */
1301 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */
1302 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */
1304 #define DMA_RB_CNTL 0xd000
1305 # define DMA_RB_ENABLE (1 << 0)
1311 #define DMA_RB_BASE 0xd004
1312 #define DMA_RB_RPTR 0xd008
1313 #define DMA_RB_WPTR 0xd00c
1315 #define DMA_RB_RPTR_ADDR_HI 0xd01c
1316 #define DMA_RB_RPTR_ADDR_LO 0xd020
1318 #define DMA_IB_CNTL 0xd024
1319 # define DMA_IB_ENABLE (1 << 0)
1322 #define DMA_IB_RPTR 0xd028
1323 #define DMA_CNTL 0xd02c
1324 # define TRAP_ENABLE (1 << 0)
1330 #define DMA_STATUS_REG 0xd034
1331 # define DMA_IDLE (1 << 0)
1332 #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044
1333 #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048
1334 #define DMA_TILING_CONFIG 0xd0b8
1335 #define DMA_MODE 0xd0bc
1337 #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \
1338 (((t) & 0x1) << 23) | \
1339 (((s) & 0x1) << 22) | \
1340 (((n) & 0xFFFFF) << 0))
1342 #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \
1343 (((vmid) & 0xF) << 20) | \
1344 (((n) & 0xFFFFF) << 0))
1349 (((n) & 0xFFFFF) << 0))
1359 #define DMA_PACKET_WRITE 0x2
1360 #define DMA_PACKET_COPY 0x3
1361 #define DMA_PACKET_INDIRECT_BUFFER 0x4
1362 #define DMA_PACKET_SEMAPHORE 0x5
1363 #define DMA_PACKET_FENCE 0x6
1364 #define DMA_PACKET_TRAP 0x7
1365 #define DMA_PACKET_SRBM_WRITE 0x9
1366 #define DMA_PACKET_CONSTANT_FILL 0xd
1367 #define DMA_PACKET_NOP 0xf