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/linux/drivers/net/phy/
H A Dmdio-open-alliance.h14 #define MDIO_OATC14_PLCA_IDVER 0xca00 /* PLCA ID and version */
15 #define MDIO_OATC14_PLCA_CTRL0 0xca01 /* PLCA Control register 0 */
16 #define MDIO_OATC14_PLCA_CTRL1 0xca02 /* PLCA Control register 1 */
17 #define MDIO_OATC14_PLCA_STATUS 0xca03 /* PLCA Status register */
18 #define MDIO_OATC14_PLCA_TOTMR 0xca04 /* PLCA TO Timer register */
19 #define MDIO_OATC14_PLCA_BURST 0xca05 /* PLCA BURST mode register */
22 #define MDIO_OATC14_PLCA_IDM 0xff00 /* PLCA MAP ID */
23 #define MDIO_OATC14_PLCA_VER 0x00ff /* PLCA MAP version */
30 #define MDIO_OATC14_PLCA_NCNT 0xff00 /* PLCA node count */
31 #define MDIO_OATC14_PLCA_ID 0x00ff /* PLCA local node ID */
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Drealtek,rtl9301-mdio.yaml27 const: 0
33 '^mdio-bus@[0-3]$':
61 reg = <0xca00 0x200>;
63 #size-cells = <0>;
65 mdio-bus@0 {
66 reg = <0>;
68 #size-cells = <0>;
70 ethernet-phy@0 {
72 reg = <0>;
79 #size-cells = <0>;
[all …]
H A Drealtek,rtl9301-switch.yaml51 'reboot@[0-9a-f]+$':
54 'i2c@[0-9a-f]+$':
57 'mdio-controller@[0-9a-f]+$':
72 reg = <0x1b000000 0x10000>;
81 reg = <0x0c 0x4>;
82 value = <0x01>;
87 reg = <0x36c 0x14>;
89 #size-cells = <0>;
91 i2c@0 {
92 reg = <0>;
[all …]
/linux/sound/soc/codecs/
H A Drt1017-sdca-sdw.h18 #define FUNC_NUM_SMART_AMP 0x04
21 #define RT1017_SDCA_ENT_PDE23 0x31
22 #define RT1017_SDCA_ENT_PDE22 0x33
23 #define RT1017_SDCA_ENT_CS21 0x21
24 #define RT1017_SDCA_ENT_SAPU29 0x29
25 #define RT1017_SDCA_ENT_XU22 0x22
26 #define RT1017_SDCA_ENT_FU 0x03
27 #define RT1017_SDCA_ENT_UDMPU21 0x02
30 #define RT1017_SDCA_CTL_FS_INDEX 0x10
31 #define RT1017_SDCA_CTL_REQ_POWER_STATE 0x01
[all …]
H A Drt1017-sdca-sdw.c27 case 0x2f55: in rt1017_sdca_readable_register()
28 case 0x3206: in rt1017_sdca_readable_register()
29 case 0xc000: in rt1017_sdca_readable_register()
30 case 0xc001: in rt1017_sdca_readable_register()
31 case 0xc022: in rt1017_sdca_readable_register()
32 case 0xc030: in rt1017_sdca_readable_register()
33 case 0xc104: in rt1017_sdca_readable_register()
34 case 0xc10b: in rt1017_sdca_readable_register()
35 case 0xc10c: in rt1017_sdca_readable_register()
36 case 0xc110: in rt1017_sdca_readable_register()
[all …]
H A Drt1318-sdw.c24 { 0xc001, 0x43 },
25 { 0xc003, 0xa2 },
26 { 0xc004, 0x44 },
27 { 0xc005, 0x44 },
28 { 0xc006, 0x33 },
29 { 0xc007, 0x64 },
30 { 0xc320, 0x20 },
31 { 0xf203, 0x18 },
32 { 0xf211, 0x00 },
33 { 0xf212, 0x26 },
[all …]
H A Drt1320-sdw.c31 { 0xc003, 0xe0 },
32 { 0xc01b, 0xfc },
33 { 0xc5c3, 0xf2 },
34 { 0xc5c2, 0x00 },
35 { 0xc5c6, 0x1
[all...]
/linux/arch/mips/boot/dts/realtek/
H A Drtl930x.dtsi16 #address-cells = <0>;
23 #size-cells = <0>;
25 cpu@0 {
28 reg = <0>;
35 #clock-cells = <0>;
41 #clock-cells = <0>;
47 reg = <0x1b000000 0x10000>;
57 reg = <0x0c 0x4>;
58 value = <0x01>;
63 reg = <0x36c 0x14>;
[all …]
/linux/drivers/dma/ti/
H A Dk3-psil-j7200.c64 PSIL_PDMA_MCASP(0x4400),
65 PSIL_PDMA_MCASP(0x4401),
66 PSIL_PDMA_MCASP(0x4402),
68 PSIL_PDMA_XY_PKT(0x4600),
69 PSIL_PDMA_XY_PKT(0x4601),
70 PSIL_PDMA_XY_PKT(0x4602),
71 PSIL_PDMA_XY_PKT(0x4603),
72 PSIL_PDMA_XY_PKT(0x4604),
73 PSIL_PDMA_XY_PKT(0x4605),
74 PSIL_PDMA_XY_PKT(0x4606),
[all …]
H A Dk3-psil-j784s4.c71 PSIL_PDMA_MCASP(0x4400),
72 PSIL_PDMA_MCASP(0x4401),
73 PSIL_PDMA_MCASP(0x4402),
74 PSIL_PDMA_MCASP(0x4403),
75 PSIL_PDMA_MCASP(0x4404),
77 PSIL_PDMA_XY_PKT(0x4600),
78 PSIL_PDMA_XY_PKT(0x4601),
79 PSIL_PDMA_XY_PKT(0x4602),
80 PSIL_PDMA_XY_PKT(0x4603),
81 PSIL_PDMA_XY_PKT(0x4604),
[all …]
H A Dk3-psil-j721e.c72 PSIL_SA2UL(0x4000, 0),
73 PSIL_SA2UL(0x4001, 0),
74 PSIL_SA2UL(0x4002, 0),
75 PSIL_SA2UL(0x4003, 0),
77 PSIL_ETHERNET(0x4100),
78 PSIL_ETHERNET(0x4101),
79 PSIL_ETHERNET(0x4102),
80 PSIL_ETHERNET(0x4103),
82 PSIL_ETHERNET(0x4200),
83 PSIL_ETHERNET(0x4201),
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dcik_reg.h27 #define CIK_DIDT_IND_INDEX 0xca00
28 #define CIK_DIDT_IND_DATA 0xca04
30 #define CIK_DC_GPIO_HPD_MASK 0x65b0
31 #define CIK_DC_GPIO_HPD_A 0x65b4
32 #define CIK_DC_GPIO_HPD_EN 0x65b8
33 #define CIK_DC_GPIO_HPD_Y 0x65bc
35 #define CIK_GRPH_CONTROL 0x6804
36 # define CIK_GRPH_DEPTH(x) (((x) & 0x3) << 0)
37 # define CIK_GRPH_DEPTH_8BPP 0
40 # define CIK_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)
[all …]
/linux/drivers/net/wireless/mediatek/mt7601u/
H A Dinit.c94 mt7601u_wr(dev, MT_USB_DMA_CFG, 0); in mt7601u_reset_csr_bbp()
96 mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0); in mt7601u_reset_csr_bbp()
142 for (i = 0; i < 16; i++) { in mt76_init_beacon_offsets()
148 for (i = 0; i < 4; i++) in mt76_init_beacon_offsets()
167 mt7601u_wr(dev, MT_AUX_CLK_CFG, 0); in mt7601u_write_mac_initvals()
169 return 0; in mt7601u_write_mac_initvals()
181 for (i = 0; i < N_WCIDS; i++) { in mt7601u_init_wcid_mem()
182 vals[i * 2] = 0xffffffff; in mt7601u_init_wcid_mem()
183 vals[i * 2 + 1] = 0x00ffffff; in mt7601u_init_wcid_mem()
210 for (i = 0; i < N_WCIDS * 2; i++) in mt7601u_init_wcid_attr_mem()
[all …]
/linux/include/linux/mfd/
H A Didt8a340_reg.h3 * Based on 5.2.0, Family Programming Guide (Sept 30, 2020)
10 #define PAGE_ADDR_BASE 0x0000
11 #define PAGE_ADDR 0x00fc
13 #define HW_REVISION 0x8180
14 #define REV_ID 0x007a
16 #define HW_DPLL_0 (0x8a00)
17 #define HW_DPLL_1 (0x8b00)
18 #define HW_DPLL_2 (0x8c00)
19 #define HW_DPLL_3 (0x8d00)
20 #define HW_DPLL_4 (0x8e00)
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dael1002.c36 AEL100X_TX_CONFIG1 = 0xc002,
37 AEL1002_PWR_DOWN_HI = 0xc011,
38 AEL1002_PWR_DOWN_LO = 0xc012,
39 AEL1002_XFI_EQL = 0xc015,
40 AEL1002_LB_EN = 0xc017,
41 AEL_OPT_SETTINGS = 0xc017,
42 AEL_I2C_CTRL = 0xc30a,
43 AEL_I2C_DATA = 0xc30b,
44 AEL_I2C_STAT = 0xc30c,
45 AEL2005_GPIO_CTRL = 0xc214,
[all …]
/linux/drivers/gpu/drm/bridge/
H A Dite-it66121.c32 #define IT66121_VENDOR_ID0_REG 0x00
33 #define IT66121_VENDOR_ID1_REG 0x01
34 #define IT66121_DEVICE_ID0_REG 0x02
35 #define IT66121_DEVICE_ID1_REG 0x03
38 #define IT66121_DEVICE_ID1_MASK GENMASK(3, 0)
40 #define IT66121_MASTER_SEL_REG 0x10
41 #define IT66121_MASTER_SEL_HOST BIT(0)
43 #define IT66121_AFE_DRV_REG 0x61
47 #define IT66121_INPUT_MODE_REG 0x70
48 #define IT66121_INPUT_MODE_RGB (0 << 6)
[all …]
/linux/sound/pci/
H A Dsonicvibes.c37 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
42 static unsigned int dmaio = 0x7a00; /* DDMA i/o address */
63 #define SV_REG_CONTROL 0x00 /* R/W: CODEC/Mixer control register */
64 #define SV_ENHANCED 0x01 /* audio mode select - enhanced mode */
65 #define SV_TEST 0x02 /* test bit */
66 #define SV_REVERB 0x04 /* reverb enable */
67 #define SV_WAVETABLE 0x08 /* wavetable active / FM active if not set */
68 #define SV_INTA 0x20 /* INTA driving - should be always 1 */
69 #define SV_RESET 0x80 /* reset chip */
70 #define SV_REG_IRQMASK 0x0
[all...]
/linux/drivers/clk/samsung/
H A Dclk-exynos4.c22 #define SRC_LEFTBUS 0x4200
23 #define DIV_LEFTBUS 0x4500
24 #define GATE_IP_LEFTBUS 0x4800
25 #define E4X12_GATE_IP_IMAGE 0x4930
26 #define CLKOUT_CMU_LEFTBUS 0x4a00
27 #define SRC_RIGHTBUS 0x8200
28 #define DIV_RIGHTBUS 0x8500
29 #define GATE_IP_RIGHTBUS 0x8800
30 #define E4X12_GATE_IP_PERIR 0x8960
31 #define CLKOUT_CMU_RIGHTBUS 0x8a00
[all …]
/linux/include/linux/
H A Dpci_ids.h15 #define PCI_CLASS_NOT_DEFINED 0x0000
16 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001
18 #define PCI_BASE_CLASS_STORAGE 0x01
19 #define PCI_CLASS_STORAGE_SCSI 0x0100
20 #define PCI_CLASS_STORAGE_IDE 0x0101
21 #define PCI_CLASS_STORAGE_FLOPPY 0x0102
22 #define PCI_CLASS_STORAGE_IPI 0x0103
23 #define PCI_CLASS_STORAGE_RAID 0x0104
24 #define PCI_CLASS_STORAGE_SATA 0x0106
25 #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h29 // base address: 0x0
30 …DIDT_SQ_CTRL0 0x0000
31 …DIDT_SQ_CTRL2 0x0002
32 …DIDT_SQ_STALL_CTRL 0x0004
33 …DIDT_SQ_TUNING_CTRL 0x0005
34 …DIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x0006
35 …DIDT_SQ_CTRL3 0x0007
36 …DIDT_SQ_STALL_PATTERN_1_2 0x0008
37 …DIDT_SQ_STALL_PATTERN_3_4 0x0009
38 …DIDT_SQ_STALL_PATTERN_5_6 0x000a
[all …]
H A Dgc_9_1_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]
H A Dgc_9_2_1_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]
H A Dgc_9_0_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]
H A Dgc_10_1_0_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x10A9
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x10B0
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
30 // base address: 0x4980
31 …SDMA0_DEC_START 0x0000
32 …ne mmSDMA0_DEC_START_BASE_IDX 0
33 …SDMA0_PG_CNTL 0x0016
34 …ne mmSDMA0_PG_CNTL_BASE_IDX 0
35 …SDMA0_PG_CTX_LO 0x0017
[all …]
H A Dgc_10_3_0_offset.h25 …SQ_DEBUG_STS_GLOBAL 0x10A9
26 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
27 …SQ_DEBUG_STS_GLOBAL2 0x10B0
28 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
29 …SQ_DEBUG 0x10B1
30 …ne mmSQ_DEBUG_BASE_IDX 0
33 // base address: 0x4980
34 …SDMA0_DEC_START 0x0000
35 …ne mmSDMA0_DEC_START_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
[all …]

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