32 #define IT66121_VENDOR_ID0_REG			0x00
33 #define IT66121_VENDOR_ID1_REG			0x01
34 #define IT66121_DEVICE_ID0_REG			0x02
35 #define IT66121_DEVICE_ID1_REG			0x03
38 #define IT66121_DEVICE_ID1_MASK			GENMASK(3, 0)
40 #define IT66121_MASTER_SEL_REG			0x10
41 #define IT66121_MASTER_SEL_HOST			BIT(0)
43 #define IT66121_AFE_DRV_REG			0x61
47 #define IT66121_INPUT_MODE_REG			0x70
48 #define IT66121_INPUT_MODE_RGB			(0 << 6)
55 #define IT66121_INPUT_CSC_REG			0x72
59 #define IT66121_INPUT_CSC_RGB_TO_YUV		0x02
60 #define IT66121_INPUT_CSC_YUV_TO_RGB		0x03
61 #define IT66121_INPUT_CSC_NO_CONV		0x00
63 #define IT66121_AFE_XP_REG			0x62
70 #define IT6610_AFE_XP_BYPASS			BIT(0)
72 #define IT66121_AFE_IP_REG			0x64
75 #define IT66121_AFE_IP_CKSEL_05			(0 << 4)
82 #define IT66121_AFE_IP_EC1			BIT(0)
84 #define IT66121_AFE_XP_EC1_REG			0x68
87 #define IT66121_SW_RST_REG			0x04
92 #define IT66121_SW_RST_HDCP			BIT(0)
94 #define IT66121_DDC_COMMAND_REG			0x15
95 #define IT66121_DDC_COMMAND_BURST_READ		0x0
96 #define IT66121_DDC_COMMAND_EDID_READ		0x3
97 #define IT66121_DDC_COMMAND_FIFO_CLR		0x9
98 #define IT66121_DDC_COMMAND_SCL_PULSE		0xA
99 #define IT66121_DDC_COMMAND_ABORT		0xF
101 #define IT66121_HDCP_REG			0x20
102 #define IT66121_HDCP_CPDESIRED			BIT(0)
105 #define IT66121_INT_STATUS1_REG			0x06
111 #define IT66121_INT_STATUS1_HPD_STATUS		BIT(0)
113 #define IT66121_DDC_HEADER_REG			0x11
114 #define IT66121_DDC_HEADER_HDCP			0x74
115 #define IT66121_DDC_HEADER_EDID			0xA0
117 #define IT66121_DDC_OFFSET_REG			0x12
118 #define IT66121_DDC_BYTE_REG			0x13
119 #define IT66121_DDC_SEGMENT_REG			0x14
120 #define IT66121_DDC_RD_FIFO_REG			0x17
122 #define IT66121_CLK_BANK_REG			0x0F
127 #define IT66121_CLK_BANK_0			0
130 #define IT66121_INT_REG				0x05
133 #define IT66121_INT_TX_CLK_OFF			BIT(0)
135 #define IT66121_INT_MASK1_REG			0x09
141 #define IT66121_INT_MASK1_HPD			BIT(0)
143 #define IT66121_INT_CLR1_REG			0x0C
151 #define IT66121_INT_CLR1_HPD			BIT(0)
153 #define IT66121_AV_MUTE_REG			0xC1
154 #define IT66121_AV_MUTE_ON			BIT(0)
157 #define IT66121_PKT_CTS_CTRL_REG		0xC5
160 #define IT66121_PKT_GEN_CTRL_REG		0xC6
161 #define IT66121_PKT_GEN_CTRL_ON			BIT(0)
164 #define IT66121_AVIINFO_DB1_REG			0x158
165 #define IT66121_AVIINFO_DB2_REG			0x159
166 #define IT66121_AVIINFO_DB3_REG			0x15A
167 #define IT66121_AVIINFO_DB4_REG			0x15B
168 #define IT66121_AVIINFO_DB5_REG			0x15C
169 #define IT66121_AVIINFO_CSUM_REG		0x15D
170 #define IT66121_AVIINFO_DB6_REG			0x15E
171 #define IT66121_AVIINFO_DB7_REG			0x15F
172 #define IT66121_AVIINFO_DB8_REG			0x160
173 #define IT66121_AVIINFO_DB9_REG			0x161
174 #define IT66121_AVIINFO_DB10_REG		0x162
175 #define IT66121_AVIINFO_DB11_REG		0x163
176 #define IT66121_AVIINFO_DB12_REG		0x164
177 #define IT66121_AVIINFO_DB13_REG		0x165
179 #define IT66121_AVI_INFO_PKT_REG		0xCD
180 #define IT66121_AVI_INFO_PKT_ON			BIT(0)
183 #define IT66121_HDMI_MODE_REG			0xC0
184 #define IT66121_HDMI_MODE_HDMI			BIT(0)
186 #define IT66121_SYS_STATUS_REG			0x0E
192 #define IT66121_SYS_STATUS_CLEAR_IRQ		BIT(0)
194 #define IT66121_DDC_STATUS_REG			0x16
202 #define IT66121_DDC_STATUS_FIFO_VALID		BIT(0)
208 #define IT66121_CLK_CTRL0_REG			0x58
211 #define IT66121_CLK_CTRL0_EXT_MCLK_128FS	(0 << 2)
215 #define IT66121_CLK_CTRL0_AUTO_IPCLK		BIT(0)
216 #define IT66121_CLK_STATUS1_REG			0x5E
217 #define IT66121_CLK_STATUS2_REG			0x5F
219 #define IT66121_AUD_CTRL0_REG			0xE0
221 #define IT66121_AUD_16BIT			(0 << 6)
227 #define IT66121_AUD_I2S				(0 << 4)
231 #define IT66121_AUD_EN_I2S0			BIT(0)
234 #define IT66121_AUD_CTRL1_REG			0xE1
235 #define IT66121_AUD_FIFOMAP_REG			0xE2
236 #define IT66121_AUD_CTRL3_REG			0xE3
237 #define IT66121_AUD_SRCVALID_FLAT_REG		0xE4
242 #define IT66121_AUD_HDAUDIO_REG			0xE5
244 #define IT66121_AUD_PKT_CTS0_REG		0x130
245 #define IT66121_AUD_PKT_CTS1_REG		0x131
246 #define IT66121_AUD_PKT_CTS2_REG		0x132
247 #define IT66121_AUD_PKT_N0_REG			0x133
248 #define IT66121_AUD_PKT_N1_REG			0x134
249 #define IT66121_AUD_PKT_N2_REG			0x135
251 #define IT66121_AUD_CHST_MODE_REG		0x191
252 #define IT66121_AUD_CHST_CAT_REG		0x192
253 #define IT66121_AUD_CHST_SRCNUM_REG		0x193
254 #define IT66121_AUD_CHST_CHTNUM_REG		0x194
255 #define IT66121_AUD_CHST_CA_FS_REG		0x198
256 #define IT66121_AUD_CHST_OFS_WL_REG		0x199
258 #define IT66121_AUD_PKT_CTS_CNT0_REG		0x1A0
259 #define IT66121_AUD_PKT_CTS_CNT1_REG		0x1A1
260 #define IT66121_AUD_PKT_CTS_CNT2_REG		0x1A2
262 #define IT66121_AUD_FS_22P05K			0x4
263 #define IT66121_AUD_FS_44P1K			0x0
264 #define IT66121_AUD_FS_88P2K			0x8
265 #define IT66121_AUD_FS_176P4K			0xC
266 #define IT66121_AUD_FS_24K			0x6
267 #define IT66121_AUD_FS_48K			0x2
268 #define IT66121_AUD_FS_96K			0xA
269 #define IT66121_AUD_FS_192K			0xE
270 #define IT66121_AUD_FS_768K			0x9
271 #define IT66121_AUD_FS_32K			0x3
272 #define IT66121_AUD_FS_OTHER			0x1
274 #define IT66121_AUD_SWL_21BIT			0xD
275 #define IT66121_AUD_SWL_24BIT			0xB
276 #define IT66121_AUD_SWL_23BIT			0x9
277 #define IT66121_AUD_SWL_22BIT			0x5
278 #define IT66121_AUD_SWL_20BIT			0x3
279 #define IT66121_AUD_SWL_17BIT			0xC
280 #define IT66121_AUD_SWL_19BIT			0x8
281 #define IT66121_AUD_SWL_18BIT			0x4
282 #define IT66121_AUD_SWL_16BIT			0x2
283 #define IT66121_AUD_SWL_NOT_INDICATED		0x0
321 		.range_min = 0x00,
322 		.range_max = 0x1FF,
324 		.selector_mask = 0x1,
325 		.selector_shift = 0,
326 		.window_start = 0x00,
327 		.window_len = 0x100,
334 	.max_register = 0x1FF,
343 	gpiod_set_value(ctx->gpio_reset, 0);  in it66121_hw_reset()
353 	return regmap_write(ctx->regmap, IT66121_AFE_DRV_REG, 0);  in it66121_fire_afe()
407 						IT66121_AFE_IP_EC1, 0);  in it66121_configure_afe()
412 						IT66121_AFE_XP_EC1_LOWCLK, 0x80);  in it66121_configure_afe()
448 				IT66121_SW_RST_REF | IT66121_SW_RST_VID, 0);  in it66121_configure_afe()
479 	return 0;  in it66121_wait_ddc_ready()
496 			   cpdesire & (~IT66121_HDCP_CPDESIRED & 0xFF));  in it66121_abort_ddc_ops()
522 	int offset = 0;  in it66121_get_edid_block()
528 	while (remain > 0) {  in it66121_get_edid_block()
575 	return 0;  in it66121_get_edid_block()
604 					IT66121_CLK_BANK_PWROFF_RCLK, 0);  in it66121_bridge_attach()
610 				IT66121_INT_TX_CLK_OFF, 0);  in it66121_bridge_attach()
615 				IT66121_AFE_DRV_PWD, 0);  in it66121_bridge_attach()
620 				IT66121_AFE_XP_PWDI | IT66121_AFE_XP_PWDPLL, 0);  in it66121_bridge_attach()
625 				IT66121_AFE_IP_PWDPLL, 0);  in it66121_bridge_attach()
630 				IT66121_AFE_DRV_RST, 0);  in it66121_bridge_attach()
653 	return 0;  in it66121_bridge_attach()
659 	unsigned int val = 0;  in it66121_set_mute()
688 	output_fmts[0] =  MEDIA_BUS_FMT_RGB888_1X24;  in it66121_bridge_atomic_get_output_bus_fmts()
706 	*num_input_fmts = 0;  in it66121_bridge_atomic_get_input_bus_fmts()
715 		input_fmts[0] = MEDIA_BUS_FMT_RGB888_2X12_LE;  in it66121_bridge_atomic_get_input_bus_fmts()
718 		input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;  in it66121_bridge_atomic_get_input_bus_fmts()
759 	return 0;  in it66121_bridge_check()
781 	if (ret < 0) {  in it66121_bridge_mode_set()
820 			      IT66121_CLK_BANK_PWROFF_TXCLK, 0)) {  in it66121_bridge_mode_set()
860 	ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG, IT66121_INT_MASK1_HPD, 0);  in it66121_bridge_hpd_enable()
971 	ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_MODE_REG, iec60958_chstat[0] & 0x7C);  in it661221_set_chstat()
979 	ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_SRCNUM_REG, iec60958_chstat[2] & 0x0F);  in it661221_set_chstat()
984 			   (iec60958_chstat[2] >> 4) & 0x0F);  in it661221_set_chstat()
998 	unsigned int audio_enable = 0;  in it661221_set_lpcm_audio()
999 	unsigned int audio_format = 0;  in it661221_set_lpcm_audio()
1017 	audio_format |= 0x40;  in it661221_set_lpcm_audio()
1032 		audio_format &= ~0x40;  in it661221_set_lpcm_audio()
1037 	audio_format |= 0x01;  in it661221_set_lpcm_audio()
1040 	ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, audio_enable & 0xF0);  in it661221_set_lpcm_audio()
1048 	ret = regmap_write(ctx->regmap, IT66121_AUD_FIFOMAP_REG, 0xE4);  in it661221_set_lpcm_audio()
1052 	ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL3_REG, 0x00);  in it661221_set_lpcm_audio()
1056 	ret = regmap_write(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 0x00);  in it661221_set_lpcm_audio()
1060 	return regmap_write(ctx->regmap, IT66121_AUD_HDAUDIO_REG, 0x00);  in it661221_set_lpcm_audio()
1098 	ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N0_REG, (u8)((n) & 0xFF));  in it661221_set_ncts()
1102 	ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N1_REG, (u8)((n >> 8) & 0xFF));  in it661221_set_ncts()
1106 	ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N2_REG, (u8)((n >> 16) & 0xF));  in it661221_set_ncts()
1112 		u8 cts_stable_cnt = 0;  in it661221_set_ncts()
1113 		unsigned int sum_cts = 0;  in it661221_set_ncts()
1114 		unsigned int cts = 0;  in it661221_set_ncts()
1115 		unsigned int last_cts = 0;  in it661221_set_ncts()
1127 			if (cts == 0) {  in it661221_set_ncts()
1139 					cts_stable_cnt = 0;  in it661221_set_ncts()
1140 					sum_cts = 0;  in it661221_set_ncts()
1151 		regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS0_REG, (u8)((last_cts) & 0xFF));  in it661221_set_ncts()
1152 		regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS1_REG, (u8)((last_cts >> 8) & 0xFF));  in it661221_set_ncts()
1153 		regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS2_REG, (u8)((last_cts >> 16) & 0x0F));  in it661221_set_ncts()
1156 	ret = regmap_write(ctx->regmap, 0xF8, 0xC3);  in it661221_set_ncts()
1160 	ret = regmap_write(ctx->regmap, 0xF8, 0xA5);  in it661221_set_ncts()
1171 					0);  in it661221_set_ncts()
1177 	return regmap_write(ctx->regmap, 0xF8, 0xFF);  in it661221_set_ncts()
1187 					0);  in it661221_audio_output_enable()
1199 					ctx->audio.ch_enable & 0xF0);  in it661221_audio_output_enable()
1216 		ret = regmap_write(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 0);  in it661221_audio_ch_enable()
1222 		ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, ctx->audio.ch_enable & 0xF0);  in it661221_audio_ch_enable()
1264 				IT66121_AUD_CTRL0_AUD_SEL, 0); // remove spdif selection  in it66121_audio_hw_params()
1313 	iec60958_chstat[0] = 0;  in it66121_audio_hw_params()
1315 		iec60958_chstat[0] |= 0x1;  in it66121_audio_hw_params()
1316 	iec60958_chstat[0] &= ~(1 << 1);  in it66121_audio_hw_params()
1317 	iec60958_chstat[1] = 0;  in it66121_audio_hw_params()
1319 	iec60958_chstat[2] |= (channels << 4) & 0xF0;  in it66121_audio_hw_params()
1355 	iec60958_chstat[4] = (((~fs) << 4) & 0xF0) | swl;  in it66121_audio_hw_params()
1371 				0);  in it66121_audio_hw_params()
1435 					0);  in it66121_audio_mute()
1452 		memset(buf, 0, len);  in it66121_audio_get_eld()
1461 	return 0;  in it66121_audio_get_eld()
1477 		.spdif = 0,  in it66121_audio_codec_init()
1486 		return 0;  in it66121_audio_codec_init()
1509 	u32 revision_id, vendor_ids[2] = { 0 }, device_ids[2] = { 0 };  in it66121_probe()
1525 	ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0);  in it66121_probe()
1568 	regmap_read(ctx->regmap, IT66121_VENDOR_ID0_REG, &vendor_ids[0]);  in it66121_probe()
1570 	regmap_read(ctx->regmap, IT66121_DEVICE_ID0_REG, &device_ids[0]);  in it66121_probe()
1577 	if ((vendor_ids[1] << 8 | vendor_ids[0]) != ctx->info->vid ||  in it66121_probe()
1578 	    (device_ids[1] << 8 | device_ids[0]) != ctx->info->pid) {  in it66121_probe()
1585 	if (client->irq > 0) {  in it66121_probe()
1592 		if (ret < 0) {  in it66121_probe()
1604 	return 0;  in it66121_probe()
1617 	.vid = 0x4954,
1618 	.pid = 0x0612,
1623 	.vid = 0xca00,
1624 	.pid = 0x0611,