Lines Matching +full:0 +full:xca00
27 #define CIK_DIDT_IND_INDEX 0xca00
28 #define CIK_DIDT_IND_DATA 0xca04
30 #define CIK_DC_GPIO_HPD_MASK 0x65b0
31 #define CIK_DC_GPIO_HPD_A 0x65b4
32 #define CIK_DC_GPIO_HPD_EN 0x65b8
33 #define CIK_DC_GPIO_HPD_Y 0x65bc
35 #define CIK_GRPH_CONTROL 0x6804
36 # define CIK_GRPH_DEPTH(x) (((x) & 0x3) << 0)
37 # define CIK_GRPH_DEPTH_8BPP 0
40 # define CIK_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)
41 # define CIK_ADDR_SURF_2_BANK 0
45 # define CIK_GRPH_Z(x) (((x) & 0x3) << 4)
46 # define CIK_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)
47 # define CIK_ADDR_SURF_BANK_WIDTH_1 0
51 # define CIK_GRPH_FORMAT(x) (((x) & 0x7) << 8)
53 # define CIK_GRPH_FORMAT_INDEXED 0
55 # define CIK_GRPH_FORMAT_ARGB1555 0
62 # define CIK_GRPH_FORMAT_ARGB8888 0
70 # define CIK_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11)
71 # define CIK_ADDR_SURF_BANK_HEIGHT_1 0
75 # define CIK_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13)
76 # define CIK_ADDR_SURF_TILE_SPLIT_64B 0
83 # define CIK_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18)
84 # define CIK_ADDR_SURF_MACRO_TILE_ASPECT_1 0
88 # define CIK_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
89 # define CIK_GRPH_ARRAY_LINEAR_GENERAL 0
93 # define CIK_GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24)
94 # define CIK_ADDR_SURF_P2 0
106 # define CIK_GRPH_MICRO_TILE_MODE(x) (((x) & 0x7) << 29)
107 # define CIK_DISPLAY_MICRO_TILING 0
112 /* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */
113 #define CIK_CUR_CONTROL 0x6998
114 # define CIK_CURSOR_EN (1 << 0)
115 # define CIK_CURSOR_MODE(x) (((x) & 0x3) << 8)
116 # define CIK_CURSOR_MONO 0
122 # define CIK_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24)
123 # define CIK_CURSOR_URGENT_ALWAYS 0
128 #define CIK_CUR_SURFACE_ADDRESS 0x699c
129 # define CIK_CUR_SURFACE_ADDRESS_MASK 0xfffff000
130 #define CIK_CUR_SIZE 0x69a0
131 #define CIK_CUR_SURFACE_ADDRESS_HIGH 0x69a4
132 #define CIK_CUR_POSITION 0x69a8
133 #define CIK_CUR_HOT_SPOT 0x69ac
134 #define CIK_CUR_COLOR1 0x69b0
135 #define CIK_CUR_COLOR2 0x69b4
136 #define CIK_CUR_UPDATE 0x69b8
137 # define CIK_CURSOR_UPDATE_PENDING (1 << 0)
142 #define CIK_ALPHA_CONTROL 0x6af0
145 #define CIK_LB_DATA_FORMAT 0x6b00
148 #define CIK_LB_DESKTOP_HEIGHT 0x6b0c
150 #define SQ_IND_INDEX 0x8DE0
151 #define SQ_CMD 0x8DEC
152 #define SQ_IND_DATA 0x8DE4
158 #define TCP_WATCH0_ADDR_H (0x32A0*4)
159 #define TCP_WATCH1_ADDR_H (0x32A3*4)
160 #define TCP_WATCH2_ADDR_H (0x32A6*4)
161 #define TCP_WATCH3_ADDR_H (0x32A9*4)
162 #define TCP_WATCH0_ADDR_L (0x32A1*4)
163 #define TCP_WATCH1_ADDR_L (0x32A4*4)
164 #define TCP_WATCH2_ADDR_L (0x32A7*4)
165 #define TCP_WATCH3_ADDR_L (0x32AA*4)
166 #define TCP_WATCH0_CNTL (0x32A2*4)
167 #define TCP_WATCH1_CNTL (0x32A5*4)
168 #define TCP_WATCH2_CNTL (0x32A8*4)
169 #define TCP_WATCH3_CNTL (0x32AB*4)
171 #define CPC_INT_CNTL 0xC2D0
173 #define CP_HQD_IQ_RPTR 0xC970u
174 #define SDMA0_RLC0_RB_CNTL 0xD400u
176 #define SDMA0_RLC0_RB_BASE 0xD404u
177 #define SDMA0_RLC0_RB_BASE_HI 0xD408u
178 #define SDMA0_RLC0_RB_RPTR 0xD40Cu
179 #define SDMA0_RLC0_RB_WPTR 0xD410u
180 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL 0xD414u
181 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0xD418u
182 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0xD41Cu
183 #define SDMA0_RLC0_RB_RPTR_ADDR_HI 0xD420u
184 #define SDMA0_RLC0_RB_RPTR_ADDR_LO 0xD424u
185 #define SDMA0_RLC0_IB_CNTL 0xD428u
186 #define SDMA0_RLC0_IB_RPTR 0xD42Cu
187 #define SDMA0_RLC0_IB_OFFSET 0xD430u
188 #define SDMA0_RLC0_IB_BASE_LO 0xD434u
189 #define SDMA0_RLC0_IB_BASE_HI 0xD438u
190 #define SDMA0_RLC0_IB_SIZE 0xD43Cu
191 #define SDMA0_RLC0_SKIP_CNTL 0xD440u
192 #define SDMA0_RLC0_CONTEXT_STATUS 0xD444u
194 #define SDMA0_RLC0_DOORBELL 0xD448u
195 #define SDMA_OFFSET(x) (x << 0)
197 #define SDMA0_RLC0_VIRTUAL_ADDR 0xD49Cu
198 #define SDMA_ATC (1 << 0)
201 #define SDMA0_RLC0_APE1_CNTL 0xD4A0u
202 #define SDMA0_RLC0_DOORBELL_LOG 0xD4A4u
203 #define SDMA0_RLC0_WATERMARK 0xD4A8u
204 #define SDMA0_CNTL 0xD010
205 #define SDMA1_CNTL 0xD810
213 ADDRESS_WATCH_REG_ADDR_HI = 0,
220 ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL,
221 ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF,
222 ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000,
225 ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF