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/linux/arch/arm/mach-davinci/
H A Dda830.c27 #define DA830_CMP12_0 0x60
28 #define DA830_CMP12_1 0x64
29 #define DA830_CMP12_2 0x68
30 #define DA830_CMP12_3 0x6c
31 #define DA830_CMP12_4 0x70
32 #define DA830_CMP12_5 0x74
33 #define DA830_CMP12_6 0x78
34 #define DA830_CMP12_7 0x7c
46 MUX_CFG(DA830, GPIO7_14, 0, 0, 0xf, 1, false)
47 MUX_CFG(DA830, RTCK, 0, 0, 0xf, 8, false)
[all …]
/linux/sound/soc/fsl/
H A Dfsl_asrc.c50 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
56 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
63 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
64 0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd,
65 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
66 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
70 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
71 0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd,
72 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
73 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
[all …]
/linux/sound/soc/mediatek/mt8192/
H A Dmt8192-reg.h26 #define BCK_INVERSE_MASK 0x1
27 #define BCK_INVERSE_MASK_SFT (0x1 << 3)
31 #define VUL12_ON_MASK 0x1
32 #define VUL12_ON_MASK_SFT (0x1 << 31)
34 #define MOD_DAI_ON_MASK 0x1
35 #define MOD_DAI_ON_MASK_SFT (0x1 << 30)
37 #define DAI_ON_MASK 0x1
38 #define DAI_ON_MASK_SFT (0x1 << 29)
40 #define DAI2_ON_MASK 0x1
41 #define DAI2_ON_MASK_SFT (0x1 << 28)
[all …]
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dpsoc_reset_conf_masks.h24 #define PSOC_RESET_CONF_PSOC_PRSTN_RST_CFG_EN_SHIFT 0
25 #define PSOC_RESET_CONF_PSOC_PRSTN_RST_CFG_EN_MASK 0x1
28 #define PSOC_RESET_CONF_PSOC_SOFT_RST_CFG_EN_SHIFT 0
29 #define PSOC_RESET_CONF_PSOC_SOFT_RST_CFG_EN_MASK 0x1
32 #define PSOC_RESET_CONF_PSOC_FW_RST_CFG_EN_SHIFT 0
33 #define PSOC_RESET_CONF_PSOC_FW_RST_CFG_EN_MASK 0x1
36 #define PSOC_RESET_CONF_PSOC_WD_RST_CFG_EN_SHIFT 0
37 #define PSOC_RESET_CONF_PSOC_WD_RST_CFG_EN_MASK 0x1
40 #define PSOC_RESET_CONF_PSOC_MNL_RST_CFG_EN_SHIFT 0
41 #define PSOC_RESET_CONF_PSOC_MNL_RST_CFG_EN_MASK 0x1
[all …]
/linux/drivers/accel/habanalabs/include/gaudi/
H A Dgaudi_masks.h15 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
16 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \
17 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0xF)))
20 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
21 (FIELD_PREP(DMA0_QM_GLBL_PROT_CQF_MASK, 0xF)) | \
22 (FIELD_PREP(DMA0_QM_GLBL_PROT_CP_MASK, 0xF)) | \
23 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
26 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
27 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
30 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dcyrus_p5020.dts30 size = <0 0x1000000>;
31 alignment = <0 0x1000000>;
34 size = <0 0x400000>;
35 alignment = <0 0x400000>;
38 size = <0 0x2000000>;
39 alignment = <0 0x2000000>;
44 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
48 ranges = <0x0 0xf 0xf4000000 0x200000>;
52 ranges = <0x0 0xf 0xf4200000 0x200000>;
56 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
H A Dmpc8572ds_36b.dts19 reg = <0xf 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
22 0x1 0x0 0xf 0xe0000000 0x08000000
23 0x2 0x0 0xf 0xffa00000 0x00040000
24 0x3 0x0 0xf 0xffdf0000 0x00008000
25 0x4 0x0 0xf 0xffa40000 0x00040000
26 0x5 0x0 0xf 0xffa80000 0x00040000
27 0x6 0x0 0xf 0xffac0000 0x00040000>;
31 ranges = <0x0 0xf 0xffe00000 0x100000>;
35 reg = <0xf 0xffe08000 0 0x1000>;
[all …]
H A Dkmcent2.dts27 size = <0 0x1000000>;
28 alignment = <0 0x1000000>;
31 size = <0 0x400000>;
32 alignment = <0 0x400000>;
35 size = <0 0x2000000>;
36 alignment = <0 0x2000000>;
41 reg = <0xf 0xfe124000 0 0x2000>;
42 ranges = <0 0 0xf 0xe8000000 0x04000000
43 1 0 0xf 0xfa000000 0x00010000
44 2 0 0xf 0xfb000000 0x00010000
[all …]
H A Dmpc8536ds_36b.dts17 #size-cells = <0>;
19 PowerPC,8536@0 {
21 reg = <0>;
28 reg = <0 0 0 0>; // Filled by U-Boot
32 reg = <0xf 0xffe05000 0 0x1000>;
34 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
35 0x2 0x0 0xf 0xffa00000 0x00040000
36 0x3 0x0 0xf 0xffdf0000 0x00008000>;
40 ranges = <0x0 0xf 0xffe00000 0x100000>;
44 reg = <0xf 0xffe08000 0 0x1000>;
[all …]
H A Dt104xd4rdb.dtsi42 size = <0 0x1000000>;
43 alignment = <0 0x1000000>;
46 size = <0 0x400000>;
47 alignment = <0 0x400000>;
50 size = <0 0x2000000>;
51 alignment = <0 0x2000000>;
56 reg = <0xf 0xfe124000 0 0x2000>;
57 ranges = <0 0 0xf 0xe8000000 0x08000000
58 2 0 0xf 0xff800000 0x00010000
59 3 0 0xf 0xffdf0000 0x00008000>;
[all …]
H A Dt104xrdb.dtsi48 size = <0 0x1000000>;
49 alignment = <0 0x1000000>;
52 size = <0 0x400000>;
53 alignment = <0 0x400000>;
56 size = <0 0x2000000>;
57 alignment = <0 0x2000000>;
62 reg = <0xf 0xfe124000 0 0x2000>;
63 ranges = <0 0 0xf 0xe8000000 0x08000000
64 2 0 0xf 0xff800000 0x00010000
65 3 0 0xf 0xffdf0000 0x00008000>;
[all …]
H A Dt208xrdb.dtsi48 size = <0 0x1000000>;
49 alignment = <0 0x1000000>;
52 size = <0 0x400000>;
53 alignment = <0 0x400000>;
56 size = <0 0x2000000>;
57 alignment = <0 0x2000000>;
62 reg = <0xf 0xfe124000 0 0x2000>;
63 ranges = <0 0 0xf 0xe8000000 0x08000000
64 2 0 0xf 0xff800000 0x00010000
65 3 0 0xf 0xffdf0000 0x00008000>;
[all …]
H A Dp1022ds_36b.dts45 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
46 0x1 0x0 0xf 0xe0000000 0x08000000
47 0x2 0x0 0xf 0xff800000 0x00040000
48 0x3 0x0 0xf 0xffdf0000 0x00008000>;
49 reg = <0xf 0xffe05000 0 0x1000>;
53 ranges = <0x0 0xf 0xffe00000 0x100000>;
57 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
58 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
59 reg = <0xf 0xffe09000 0 0x1000>;
60 pcie@0 {
[all …]
H A Dkmcoge4.dts30 size = <0 0x1000000>;
31 alignment = <0 0x1000000>;
34 size = <0 0x400000>;
35 alignment = <0 0x400000>;
38 size = <0 0x2000000>;
39 alignment = <0 0x2000000>;
44 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
48 ranges = <0x0 0xf 0xf4000000 0x200000>;
52 ranges = <0x0 0xf 0xf4200000 0x200000>;
56 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
H A Dp1021rdb-pc_36b.dts45 reg = <0xf 0xffe05000 0 0x1000>;
48 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
49 0x1 0x0 0xf 0xff800000 0x00040000
50 0x2 0x0 0xf 0xffb00000 0x00020000>;
54 ranges = <0x0 0xf 0xffe00000 0x100000>;
58 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
59 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
60 reg = <0xf 0xffe09000 0 0x1000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xa0000000
[all …]
/linux/fs/xfs/scrub/
H A Dxfile.c57 struct xfile *xf; in xfile_create() local
60 xf = kmalloc(sizeof(struct xfile), XCHK_GFP_FLAGS); in xfile_create()
61 if (!xf) in xfile_create()
64 xf->file = shmem_kernel_file_setup(description, isize, VM_NORESERVE); in xfile_create()
65 if (IS_ERR(xf->file)) { in xfile_create()
66 error = PTR_ERR(xf->file); in xfile_create()
70 inode = file_inode(xf->file); in xfile_create()
79 trace_xfile_create(xf); in xfile_create()
81 *xfilep = xf; in xfile_create()
82 return 0; in xfile_create()
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_aic.c25 0, 3, 9, 15, 21, 27
67 for (i = index - 1; i >= 0; i--) { in ar9003_aic_find_valid()
73 if ((i >= ATH_AIC_MAX_BT_CHANNEL) || (i < 0)) in ar9003_aic_find_valid()
80 * type 0: aic_lin_table, 1: com_att_db_table
86 if (type == 0) { in ar9003_aic_find_index()
87 for (i = ATH_AIC_MAX_AIC_LIN_TABLE - 1; i >= 0; i--) { in ar9003_aic_find_index()
92 for (i = 0; i < ATH_AIC_MAX_COM_ATT_DB_TABLE; i++) { in ar9003_aic_find_index()
111 REG_WRITE(ah, AR_PHY_BT_COEX_4, 0x2c200a00); in ar9003_aic_gain_table()
112 REG_WRITE(ah, AR_PHY_BT_COEX_5, 0x5c4e4438); in ar9003_aic_gain_table()
115 aic_atten_word[0] = (0x1 & 0xf) << 14 | (0x1f & 0x1f) << 9 | (0x0 & 0xf) << 5 | in ar9003_aic_gain_table()
[all …]
/linux/sound/soc/mediatek/mt8183/
H A Dmt8183-reg.h12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON1 0x0004
14 #define AUDIO_TOP_CON3 0x000c
15 #define AFE_DAC_CON0 0x0010
16 #define AFE_DAC_CON1 0x0014
17 #define AFE_I2S_CON 0x0018
18 #define AFE_DAIBT_CON0 0x001c
19 #define AFE_CONN0 0x0020
20 #define AFE_CONN1 0x0024
21 #define AFE_CONN2 0x0028
[all …]
/linux/arch/sh/boards/mach-sh03/
H A Drtc.c19 #define RTC_BASE 0xb0000000
20 #define RTC_SEC1 (RTC_BASE + 0)
48 sec = (__raw_readb(RTC_SEC1) & 0xf) + (__raw_readb(RTC_SEC10) & 0x7) * 10; in sh03_rtc_gettimeofday()
49 min = (__raw_readb(RTC_MIN1) & 0xf) + (__raw_readb(RTC_MIN10) & 0xf) * 10; in sh03_rtc_gettimeofday()
50 hour = (__raw_readb(RTC_HOU1) & 0xf) + (__raw_readb(RTC_HOU10) & 0xf) * 10; in sh03_rtc_gettimeofday()
51 day = (__raw_readb(RTC_DAY1) & 0xf) + (__raw_readb(RTC_DAY10) & 0xf) * 10; in sh03_rtc_gettimeofday()
52 mon = (__raw_readb(RTC_MON1) & 0xf) + (__raw_readb(RTC_MON10) & 0xf) * 10; in sh03_rtc_gettimeofday()
53 year = (__raw_readb(RTC_YEA1) & 0xf) + (__raw_readb(RTC_YEA10) & 0xf) * 10 in sh03_rtc_gettimeofday()
54 + (__raw_readb(RTC_YEA100 ) & 0xf) * 100 in sh03_rtc_gettimeofday()
55 + (__raw_readb(RTC_YEA1000) & 0xf) * 1000; in sh03_rtc_gettimeofday()
[all …]
/linux/drivers/gpu/drm/tegra/
H A Dsor.h9 #define SOR_CTXSW 0x00
11 #define SOR_SUPER_STATE0 0x01
13 #define SOR_SUPER_STATE1 0x02
16 #define SOR_SUPER_STATE_HEAD_MODE_MASK (3 << 0)
17 #define SOR_SUPER_STATE_HEAD_MODE_AWAKE (2 << 0)
18 #define SOR_SUPER_STATE_HEAD_MODE_SNOOZE (1 << 0)
19 #define SOR_SUPER_STATE_HEAD_MODE_SLEEP (0 << 0)
21 #define SOR_STATE0 0x03
23 #define SOR_STATE1 0x04
24 #define SOR_STATE_ASY_PIXELDEPTH_MASK (0xf << 17)
[all …]
/linux/drivers/net/ethernet/amd/
H A Damd8111e.h20 3.0.0
32 … 00011010b is written into the same byte, bits 1,3 and 4 will be cleared to 0 and the other bits w…
39 #define ASF_STAT 0x00 /* ASF status register */
40 #define CHIPID 0x04 /* Chip ID register */
41 #define MIB_DATA 0x10 /* MIB data register */
42 #define MIB_ADDR 0x14 /* MIB address register */
43 #define STAT0 0x30 /* Status0 register */
44 #define INT0 0x38 /* Interrupt0 register */
45 #define INTEN0 0x40 /* Interrupt0 enable register*/
46 #define CMD0 0x48 /* Command0 register */
[all …]
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn10/
H A Ddcn10_mpc.c68 REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
70 REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
72 REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
155 if (top_sel == 0xf && opp_id == 0xf && idle) in mpc1_is_mpcc_idle()
169 if (top_sel == 0xf) { in mpc1_assert_mpcc_idle_before_connect()
174 ASSERT(mpc_busy == 0); in mpc1_assert_mpcc_idle_before_connect()
229 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id); in mpc1_insert_plane()
233 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); in mpc1_insert_plane()
236 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id); in mpc1_insert_plane()
237 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id); in mpc1_insert_plane()
[all …]
/linux/arch/arm/probes/kprobes/
H A Dactions-arm.c32 * instruction in insn[0]. In insn[1] is a
73 int rt = (insn >> 12) & 0xf; in emulate_ldrdstrd()
74 int rn = (insn >> 16) & 0xf; in emulate_ldrdstrd()
75 int rm = insn & 0xf; in emulate_ldrdstrd()
86 : "0" (rtv), "1" (rt2v), "2" (rnv), "r" (rmv), in emulate_ldrdstrd()
102 int rt = (insn >> 12) & 0xf; in emulate_ldr()
103 int rn = (insn >> 16) & 0xf; in emulate_ldr()
104 int rm = insn & 0xf; in emulate_ldr()
133 int rt = (insn >> 12) & 0xf; in emulate_str()
134 int rn = (insn >> 16) & 0xf; in emulate_str()
[all …]
/linux/drivers/ssb/
H A Ddriver_chipcommon_pmu.c52 u8 xf; /* Crystal frequency value for PMU control */ member
58 { .freq = 12000, .xf = 1, .wb_int = 73, .wb_frac = 349525, },
59 { .freq = 13000, .xf = 2, .wb_int = 67, .wb_frac = 725937, },
60 { .freq = 14400, .xf = 3, .wb_int = 61, .wb_frac = 116508, },
61 { .freq = 15360, .xf = 4, .wb_int = 57, .wb_frac = 305834, },
62 { .freq = 16200, .xf = 5, .wb_int = 54, .wb_frac = 336579, },
63 { .freq = 16800, .xf = 6, .wb_int = 52, .wb_frac = 399457, },
64 { .freq = 19200, .xf = 7, .wb_int = 45, .wb_frac = 873813, },
65 { .freq = 19800, .xf = 8, .wb_int = 44, .wb_frac = 466033, },
66 { .freq = 20000, .xf = 9, .wb_int = 44, .wb_frac = 0, },
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_0_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
[all …]

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