Lines Matching +full:0 +full:xf
15 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
16 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \
17 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0xF)))
20 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
21 (FIELD_PREP(DMA0_QM_GLBL_PROT_CQF_MASK, 0xF)) | \
22 (FIELD_PREP(DMA0_QM_GLBL_PROT_CP_MASK, 0xF)) | \
23 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
26 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
27 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
30 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
31 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \
32 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))
35 (FIELD_PREP(MME0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
36 (FIELD_PREP(MME0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \
37 (FIELD_PREP(MME0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))
40 (FIELD_PREP(TPC0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
41 (FIELD_PREP(TPC0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \
42 (FIELD_PREP(TPC0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))
45 (FIELD_PREP(NIC0_QM0_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
46 (FIELD_PREP(NIC0_QM0_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \
47 (FIELD_PREP(NIC0_QM0_GLBL_CFG0_CP_EN_MASK, 0xF)))
50 (FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \
51 (FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \
52 (FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0x10)) | \
53 (FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1)))
56 (FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \
57 (FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \
58 (FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0xF)) | \
59 (FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1)))
62 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
63 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0xF)) | \
64 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0xF)))
67 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
68 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0xF)) | \
69 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0xF)) | \
70 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))
73 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
74 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \
75 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))
78 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
79 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \
80 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)) | \
81 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))
84 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
85 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \
86 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))
89 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
90 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \
91 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)) | \
92 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))
95 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
96 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \
97 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))
100 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
101 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \
102 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)) | \
103 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))
106 (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
107 (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0xF)) | \
108 (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0xF)))
111 (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
112 (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0xF)) | \
113 (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0xF)) | \
114 (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))
116 #define QMAN_CGM1_PWR_GATE_EN (FIELD_PREP(DMA0_QM_CGM_CFG1_MASK_TH_MASK, 0xA))
119 #define CFG_RST_L_PSOC_MASK BIT_MASK(0)
156 #define CFG_RST_H_TPC_7_MASK BIT_MASK(0)
190 #define UNIT_RST_L_PSOC_SHIFT 0
223 #define UNIT_RST_H_MME_3_SHIFT 0
283 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0
284 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_MASK 0x3
286 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_MASK 0x30
288 #define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_MASK 0x100
290 #define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_MASK 0x1000
292 #define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_MASK 0x10000
294 #define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_MASK 0x300000
320 #define MME0_CTRL_ARCH_STATUS_SB_A_EMPTY_MASK 0x80
321 #define MME0_CTRL_ARCH_STATUS_SB_B_EMPTY_MASK 0x100
322 #define MME0_CTRL_ARCH_STATUS_WBC_AXI_IDLE_MASK 0x1000
356 #define RAZWI_INITIATOR_AXI_ID_MASK 0xF
358 #define RAZWI_INITIATOR_X_MASK 0xF
360 #define RAZWI_INITIATOR_Y_MASK 0x7
379 #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_0 RAZWI_INITIATOR_ID_X_Y(0, 1)
381 #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_1 RAZWI_INITIATOR_ID_X_Y(0, 2)
383 #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_0 RAZWI_INITIATOR_ID_X_Y(0, 3)
385 #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_1 RAZWI_INITIATOR_ID_X_Y(0, 4)
397 #define PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK 0x1
398 #define PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK 0x2
399 #define PSOC_ETR_AXICTL_WRBURSTLEN_MASK 0xF00
402 #define STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0
403 #define STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF
405 #define STLB_CACHE_INV_INDEX_MASK_MASK 0xFF00
407 #define MME_ACC_ACC_STALL_R_SHIFT 0
408 #define MME_SBAB_SB_STALL_R_SHIFT 0
410 #define PCIE_WRAP_LBW_PROT_OVR_RD_EN_MASK 0x700
411 #define PCIE_WRAP_LBW_PROT_OVR_WR_EN_MASK 0x7000
413 #define PCIE_WRAP_LBW_DRAIN_CFG_EN_SHIFT 0
414 #define PCIE_WRAP_HBW_DRAIN_CFG_EN_SHIFT 0
417 #define DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT 0
418 #define DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_MASK 0x1
420 #define DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_MASK 0x2
422 #define DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT 0
423 #define DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT 0
424 #define DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT 0
425 #define DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT 0
427 #define IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT 0
428 #define IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT 0
430 #define IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT 0
431 #define IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT 0
434 #define MMU_UP_PAGE_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF
435 #define MMU_UP_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000
438 #define MMU_UP_ACCESS_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF
439 #define MMU_UP_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000
441 #define QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1
442 #define QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2
443 #define QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4
450 #define PCIE_AUX_FLR_CTRL_HW_CTRL_MASK 0x1
451 #define PCIE_AUX_FLR_CTRL_INT_MASK_MASK 0x2
453 #define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_VALID_SHIFT 0
454 #define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_VALID_MASK 0x1
456 #define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_PENDING_MASK 0x1FE
457 #define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SID_SHIFT 0
458 #define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SID_MASK 0xFF
460 #define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_MASK_MASK 0xFF00
462 #define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOP_MASK 0x10000
464 #define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOD_MASK 0xFFFE0000
466 #define TPC0_QM_CP_STS_0_FENCE_ID_MASK 0x300000
468 #define TPC0_QM_CP_STS_0_FENCE_IN_PROGRESS_MASK 0x400000