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/linux/arch/sh/kernel/cpu/sh3/
H A Dsetup-sh7710.c19 UNUSED = 0,
33 INTC_VECT(DMAC1, 0x800), INTC_VECT(DMAC1, 0x820),
34 INTC_VECT(DMAC1, 0x840), INTC_VECT(DMAC1, 0x860),
35 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
36 INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
37 INTC_VECT(SCIF1, 0x900), INTC_VECT(SCIF1, 0x920),
38 INTC_VECT(SCIF1, 0x940), INTC_VECT(SCIF1, 0x960),
39 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0),
41 INTC_VECT(IPSEC, 0xbe0),
43 INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20),
[all …]
H A Dsetup-sh7705.c20 UNUSED = 0,
36 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
37 INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
38 INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
39 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
40 INTC_VECT(SCIF0, 0x8e0),
41 INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
42 INTC_VECT(SCIF2, 0x960),
43 INTC_VECT(ADC_ADI, 0x980),
44 INTC_VECT(USB, 0xa20), INTC_VECT(USB, 0xa40),
[all …]
H A Dsetup-sh770x.c24 UNUSED = 0,
36 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
37 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
38 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
39 INTC_VECT(RTC, 0x4c0),
40 INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500),
41 INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540),
42 INTC_VECT(WDT, 0x560),
43 INTC_VECT(REF, 0x580),
44 INTC_VECT(REF, 0x5a0),
[all …]
/linux/include/linux/
H A Dahci-remap.h7 #define AHCI_VSCAP 0xa4
8 #define AHCI_REMAP_CAP 0x800
11 #define AHCI_REMAP_N_DCC 0x880
21 return AHCI_REMAP_N_DCC + i * 0x80; in ahci_remap_dcc()
/linux/arch/sh/kernel/cpu/sh4a/
H A Dsetup-sh7785.c27 DEFINE_RES_MEM(0xffea0000, 0x100),
28 DEFINE_RES_IRQ(evt2irq(0x700)),
33 .id = 0,
48 DEFINE_RES_MEM(0xffeb0000, 0x100),
49 DEFINE_RES_IRQ(evt2irq(0x780)),
69 DEFINE_RES_MEM(0xffec0000, 0x100),
70 DEFINE_RES_IRQ(evt2irq(0x980)),
90 DEFINE_RES_MEM(0xffed0000, 0x100),
91 DEFINE_RES_IRQ(evt2irq(0x9a0)),
111 DEFINE_RES_MEM(0xffee0000, 0x100),
[all …]
H A Dsetup-shx3.c20 * This intentionally only registers SCIF ports 0, 1, and 3. SCIF 2
34 DEFINE_RES_MEM(0xffc30000, 0x100),
35 DEFINE_RES_IRQ(evt2irq(0x700)),
36 DEFINE_RES_IRQ(evt2irq(0x720)),
37 DEFINE_RES_IRQ(evt2irq(0x760)),
38 DEFINE_RES_IRQ(evt2irq(0x740)),
43 .id = 0,
57 DEFINE_RES_MEM(0xffc40000, 0x100),
58 DEFINE_RES_IRQ(evt2irq(0x780)),
59 DEFINE_RES_IRQ(evt2irq(0x7a0)),
[all …]
/linux/arch/sh/kernel/cpu/sh4/
H A Dsetup-sh7760.c17 UNUSED = 0,
44 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
45 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
46 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
47 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
48 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
49 INTC_VECT(DMAC, 0x6c0),
50 INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820),
51 INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860),
52 INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920),
[all …]
/linux/arch/sh/include/cpu-sh4a/cpu/
H A Ddma.h9 #define DMTE0_IRQ evt2irq(0x800)
10 #define DMTE4_IRQ evt2irq(0xb80)
11 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
12 #define SH_DMAC_BASE0 0xFE008020
14 #define DMTE0_IRQ evt2irq(0x800)
15 #define DMTE4_IRQ evt2irq(0xb80)
16 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
17 #define SH_DMAC_BASE0 0xFE008020
19 #define DMTE0_IRQ evt2irq(0x640)
20 #define DMTE4_IRQ evt2irq(0x780)
[all …]
/linux/drivers/clk/sophgo/
H A Dclk-cv1800.h14 #define REG_PLL_G2_CTRL 0x800
15 #define REG_PLL_G2_STATUS 0x804
16 #define REG_MIPIMPLL_CSR 0x808
17 #define REG_A0PLL_CSR 0x80C
18 #define REG_DISPPLL_CSR 0x810
19 #define REG_CAM0PLL_CSR 0x814
20 #define REG_CAM1PLL_CSR 0x818
21 #define REG_PLL_G2_SSC_SYN_CTRL 0x840
22 #define REG_A0PLL_SSC_SYN_CTRL 0x850
23 #define REG_A0PLL_SSC_SYN_SET 0x854
[all …]
/linux/Documentation/devicetree/bindings/media/
H A Dqcom,qcm2290-venus.yaml76 reg = <0x5a00000 0xf0000>;
104 iommus = <&apps_smmu 0x860 0x0>,
105 <&apps_smmu 0x880 0x0>;
/linux/include/dt-bindings/pinctrl/
H A Dam33xx.h18 #define SLEWCTRL_FAST 0
30 #define PIN_OUTPUT_PULLDOWN 0
43 #define AM335X_PIN_OFFSET_MIN 0x0800U
45 #define AM335X_PIN_GPMC_AD0 0x800
46 #define AM335X_PIN_GPMC_AD1 0x804
47 #define AM335X_PIN_GPMC_AD2 0x808
48 #define AM335X_PIN_GPMC_AD3 0x80c
49 #define AM335X_PIN_GPMC_AD4 0x810
50 #define AM335X_PIN_GPMC_AD5 0x814
51 #define AM335X_PIN_GPMC_AD6 0x818
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Ddra74x-mmc-iodelay.dtsi35 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
36 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
37 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
38 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
39 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
40 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
46 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
47 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
48 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
49 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
H A Ddra76x-mmc-iodelay.dtsi32 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
33 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
34 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
35 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
36 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
37 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
43 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
44 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
45 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
46 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
/linux/arch/sh/boards/mach-kfr2r09/
H A Dsetup.c49 #define DRVCRB 0xA405018C
55 .offset = 0,
73 [0] = {
75 .start = 0x00000000,
76 .end = 0x03ffffff,
91 [0] = {
93 .start = 0x10000000,
94 .end = 0x1001ffff,
111 KEY_1, KEY_2, KEY_3, 0, KEY_UP,
112 KEY_4, KEY_5, KEY_6, 0, KEY_LEFT,
[all …]
/linux/arch/arm/mach-s3c/
H A Dregs-gpio-s3c64xx.h19 #define S3C64XX_GPA_BASE S3C64XX_GPIOREG(0x0000)
20 #define S3C64XX_GPB_BASE S3C64XX_GPIOREG(0x0020)
21 #define S3C64XX_GPC_BASE S3C64XX_GPIOREG(0x0040)
22 #define S3C64XX_GPD_BASE S3C64XX_GPIOREG(0x0060)
23 #define S3C64XX_GPE_BASE S3C64XX_GPIOREG(0x0080)
24 #define S3C64XX_GPF_BASE S3C64XX_GPIOREG(0x00A0)
25 #define S3C64XX_GPG_BASE S3C64XX_GPIOREG(0x00C0)
26 #define S3C64XX_GPH_BASE S3C64XX_GPIOREG(0x00E0)
27 #define S3C64XX_GPI_BASE S3C64XX_GPIOREG(0x0100)
28 #define S3C64XX_GPJ_BASE S3C64XX_GPIOREG(0x0120)
[all …]
/linux/drivers/media/platform/sunxi/sun8i-di/
H A Dsun8i-di.h20 #define DEINTERLACE_MOD_ENABLE 0x00
21 #define DEINTERLACE_MOD_ENABLE_EN BIT(0)
23 #define DEINTERLACE_FRM_CTRL 0x04
24 #define DEINTERLACE_FRM_CTRL_REG_READY BIT(0)
30 #define DEINTERLACE_BYPASS 0x08
33 #define DEINTERLACE_AGTH_SEL 0x0c
36 #define DEINTERLACE_LINT_CTRL 0x10
37 #define DEINTERLACE_TRD_PRELUMA 0x1c
38 #define DEINTERLACE_BUF_ADDR0 0x20
39 #define DEINTERLACE_BUF_ADDR1 0x24
[all …]
/linux/include/linux/mfd/
H A Drz-mtu3.h13 #define RZ_MTU3_TSTRA 0x080 /* Timer start register A */
14 #define RZ_MTU3_TSTRB 0x880 /* Timer start register B */
17 #define RZ_MTU3_TDDRA 0x016 /* Timer dead time data register A */
18 #define RZ_MTU3_TDDRB 0x816 /* Timer dead time data register B */
19 #define RZ_MTU3_TCDRA 0x014 /* Timer cycle data register A */
20 #define RZ_MTU3_TCDRB 0x814 /* Timer cycle data register B */
21 #define RZ_MTU3_TCBRA 0x022 /* Timer cycle buffer register A */
22 #define RZ_MTU3_TCBRB 0x822 /* Timer cycle buffer register B */
23 #define RZ_MTU3_TCNTSA 0x020 /* Timer subcounter A */
24 #define RZ_MTU3_TCNTSB 0x820 /* Timer subcounter B */
[all …]
/linux/drivers/net/dsa/
H A Drzn1_a5psw.h18 #define A5PSW_REVISION 0x0
19 #define A5PSW_PORT_OFFSET(port) (0x400 * (port))
21 #define A5PSW_PORT_ENA 0x8
26 #define A5PSW_UCAST_DEF_MASK 0xC
28 #define A5PSW_VLAN_VERIFY 0x10
29 #define A5PSW_VLAN_VERI_SHIFT 0
32 #define A5PSW_BCAST_DEF_MASK 0x14
33 #define A5PSW_MCAST_DEF_MASK 0x18
35 #define A5PSW_INPUT_LEARN 0x1C
39 #define A5PSW_MGMT_CFG 0x20
[all …]
/linux/drivers/nvmem/
H A Dvf610-ocotp.c23 #define OCOTP_CTRL_REG 0x00
24 #define OCOTP_CTRL_SET 0x04
25 #define OCOTP_CTRL_CLR 0x08
26 #define OCOTP_TIMING 0x10
27 #define OCOTP_DATA 0x20
28 #define OCOTP_READ_CTRL_REG 0x30
29 #define OCOTP_READ_FUSE_DATA 0x40
33 #define OCOTP_CTRL_WR_UNLOCK_KEY 0x3E77
35 #define OCOTP_CTRL_ADDR 0
36 #define OCOTP_CTRL_ADDR_MASK GENMASK(6, 0)
[all …]
/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sdm670-mdss.yaml42 "^display-controller@[0-9a-f]+$":
50 "^displayport-controller@[0-9a-f]+$":
58 "^dsi@[0-9a-f]+$":
67 "^phy@[0-9a-f]+$":
91 reg = <0x0ae00000 0x1000>;
103 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>,
104 <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>;
107 iommus = <&apps_smmu 0x880 0x8>,
108 <&apps_smmu 0xc80 0x8>;
116 reg = <0x0ae01000 0x8f000>,
[all …]
H A Dqcom,sdm845-mdss.yaml43 "^display-controller@[0-9a-f]+$":
51 "^displayport-controller@[0-9a-f]+$":
59 "^dsi@[0-9a-f]+$":
69 "^phy@[0-9a-f]+$":
94 reg = <0x0ae00000 0x1000>;
106 iommus = <&apps_smmu 0x880 0x8>,
107 <&apps_smmu 0xc80 0x8>;
112 reg = <0x0ae01000 0x8f000>,
113 <0x0aeb0000 0x2008>;
124 interrupts = <0>;
[all …]
/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_backend.h20 #define SUN4I_BACKEND_MODCTL_REG 0x800
24 #define SUN4I_BACKEND_MODCTL_OUT_LCD0 (0 << 20)
34 #define SUN4I_BACKEND_MODCTL_DEBE_EN BIT(0)
36 #define SUN4I_BACKEND_BACKCOLOR_REG 0x804
39 #define SUN4I_BACKEND_DISSIZE_REG 0x808
40 #define SUN4I_BACKEND_DISSIZE(w, h) (((((h) - 1) & 0xffff) << 16) | \
41 (((w) - 1) & 0xffff))
43 #define SUN4I_BACKEND_LAYSIZE_REG(l) (0x810 + (0x4 * (l)))
44 #define SUN4I_BACKEND_LAYSIZE(w, h) (((((h) - 1) & 0x1fff) << 16) | \
45 (((w) - 1) & 0x1fff))
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/nic/
H A Dotx2_reg.h14 #define RVU_PF_VFX_PFVF_MBOX0 (0x00000)
15 #define RVU_PF_VFX_PFVF_MBOX1 (0x00008)
16 #define RVU_PF_VFX_PFVF_MBOXX(a, b) (0x0 | (a) << 12 | (b) << 3)
17 #define RVU_PF_VF_BAR4_ADDR (0x10)
18 #define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3)
19 #define RVU_PF_VFME_STATUSX(a) (0x800 | (a) << 3)
20 #define RVU_PF_VFTRPENDX(a) (0x820 | (a) << 3)
21 #define RVU_PF_VFTRPEND_W1SX(a) (0x840 | (a) << 3)
22 #define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3)
23 #define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8A0 | (a) << 3)
[all …]
/linux/arch/alpha/kernel/
H A Dsys_ruffian.c39 *(vulp)PYXIS_INT_HILO = 0x000000c0UL; mb(); in ruffian_init_irq()
40 *(vulp)PYXIS_INT_CNFG = 0x00002064UL; mb(); /* all clear */ in ruffian_init_irq()
42 outb(0x11,0xA0); in ruffian_init_irq()
43 outb(0x08,0xA1); in ruffian_init_irq()
44 outb(0x02,0xA1); in ruffian_init_irq()
45 outb(0x01,0xA1); in ruffian_init_irq()
46 outb(0xFF,0xA1); in ruffian_init_irq()
48 outb(0x11,0x20); in ruffian_init_irq()
49 outb(0x00,0x21); in ruffian_init_irq()
50 outb(0x04,0x21); in ruffian_init_irq()
[all …]
/linux/arch/arm/boot/dts/sunplus/
H A Dsunplus-sp7021.dtsi23 #clock-cells = <0>;
33 ranges = <0 0x9c000000 0x400000>;
38 reg = <0x4 0x28>,
39 <0x200 0x44>,
40 <0x268 0x04>;
47 reg = <0x780 0x80>, <0xa80 0x80>;
54 reg = <0xaf00 0x34>, <0xaf80 0x58>;
62 reg = <0x14 0x3>;
65 reg = <0x18 0x2>;
68 reg = <0x34 0x6>;
[all …]

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