1*c6ff132dSArnd Bergmann /* SPDX-License-Identifier: GPL-2.0 */ 2*c6ff132dSArnd Bergmann /* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h 3*c6ff132dSArnd Bergmann * 4*c6ff132dSArnd Bergmann * Copyright 2008 Openmoko, Inc. 5*c6ff132dSArnd Bergmann * Copyright 2008 Simtec Electronics 6*c6ff132dSArnd Bergmann * Ben Dooks <ben@simtec.co.uk> 7*c6ff132dSArnd Bergmann * http://armlinux.simtec.co.uk/ 8*c6ff132dSArnd Bergmann * 9*c6ff132dSArnd Bergmann * S3C64XX - GPIO register definitions 10*c6ff132dSArnd Bergmann */ 11*c6ff132dSArnd Bergmann 12*c6ff132dSArnd Bergmann #ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H 13*c6ff132dSArnd Bergmann #define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__ 14*c6ff132dSArnd Bergmann 15*c6ff132dSArnd Bergmann /* Base addresses for each of the banks */ 16*c6ff132dSArnd Bergmann 17*c6ff132dSArnd Bergmann #define S3C64XX_GPIOREG(reg) (S3C64XX_VA_GPIO + (reg)) 18*c6ff132dSArnd Bergmann 19*c6ff132dSArnd Bergmann #define S3C64XX_GPA_BASE S3C64XX_GPIOREG(0x0000) 20*c6ff132dSArnd Bergmann #define S3C64XX_GPB_BASE S3C64XX_GPIOREG(0x0020) 21*c6ff132dSArnd Bergmann #define S3C64XX_GPC_BASE S3C64XX_GPIOREG(0x0040) 22*c6ff132dSArnd Bergmann #define S3C64XX_GPD_BASE S3C64XX_GPIOREG(0x0060) 23*c6ff132dSArnd Bergmann #define S3C64XX_GPE_BASE S3C64XX_GPIOREG(0x0080) 24*c6ff132dSArnd Bergmann #define S3C64XX_GPF_BASE S3C64XX_GPIOREG(0x00A0) 25*c6ff132dSArnd Bergmann #define S3C64XX_GPG_BASE S3C64XX_GPIOREG(0x00C0) 26*c6ff132dSArnd Bergmann #define S3C64XX_GPH_BASE S3C64XX_GPIOREG(0x00E0) 27*c6ff132dSArnd Bergmann #define S3C64XX_GPI_BASE S3C64XX_GPIOREG(0x0100) 28*c6ff132dSArnd Bergmann #define S3C64XX_GPJ_BASE S3C64XX_GPIOREG(0x0120) 29*c6ff132dSArnd Bergmann #define S3C64XX_GPK_BASE S3C64XX_GPIOREG(0x0800) 30*c6ff132dSArnd Bergmann #define S3C64XX_GPL_BASE S3C64XX_GPIOREG(0x0810) 31*c6ff132dSArnd Bergmann #define S3C64XX_GPM_BASE S3C64XX_GPIOREG(0x0820) 32*c6ff132dSArnd Bergmann #define S3C64XX_GPN_BASE S3C64XX_GPIOREG(0x0830) 33*c6ff132dSArnd Bergmann #define S3C64XX_GPO_BASE S3C64XX_GPIOREG(0x0140) 34*c6ff132dSArnd Bergmann #define S3C64XX_GPP_BASE S3C64XX_GPIOREG(0x0160) 35*c6ff132dSArnd Bergmann #define S3C64XX_GPQ_BASE S3C64XX_GPIOREG(0x0180) 36*c6ff132dSArnd Bergmann 37*c6ff132dSArnd Bergmann /* SPCON */ 38*c6ff132dSArnd Bergmann 39*c6ff132dSArnd Bergmann #define S3C64XX_SPCON S3C64XX_GPIOREG(0x1A0) 40*c6ff132dSArnd Bergmann 41*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_CAM_MASK (0x3 << 30) 42*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_CAM_SHIFT (30) 43*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_CAM_2mA (0x0 << 30) 44*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_CAM_4mA (0x1 << 30) 45*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_CAM_7mA (0x2 << 30) 46*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_CAM_9mA (0x3 << 30) 47*c6ff132dSArnd Bergmann 48*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_HSSPI_MASK (0x3 << 28) 49*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT (28) 50*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_HSSPI_2mA (0x0 << 28) 51*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_HSSPI_4mA (0x1 << 28) 52*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_HSSPI_7mA (0x2 << 28) 53*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_HSSPI_9mA (0x3 << 28) 54*c6ff132dSArnd Bergmann 55*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_HSMMC_MASK (0x3 << 26) 56*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT (26) 57*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_HSMMC_2mA (0x0 << 26) 58*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_HSMMC_4mA (0x1 << 26) 59*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_HSMMC_7mA (0x2 << 26) 60*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_HSMMC_9mA (0x3 << 26) 61*c6ff132dSArnd Bergmann 62*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_LCD_MASK (0x3 << 24) 63*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_LCD_SHIFT (24) 64*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_LCD_2mA (0x0 << 24) 65*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_LCD_4mA (0x1 << 24) 66*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_LCD_7mA (0x2 << 24) 67*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_LCD_9mA (0x3 << 24) 68*c6ff132dSArnd Bergmann 69*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_MODEM_MASK (0x3 << 22) 70*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_MODEM_SHIFT (22) 71*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_MODEM_2mA (0x0 << 22) 72*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_MODEM_4mA (0x1 << 22) 73*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_MODEM_7mA (0x2 << 22) 74*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_MODEM_9mA (0x3 << 22) 75*c6ff132dSArnd Bergmann 76*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_nRSTOUT_OEN (1 << 21) 77*c6ff132dSArnd Bergmann 78*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_SPICLK1_MASK (0x3 << 18) 79*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT (18) 80*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_SPICLK1_2mA (0x0 << 18) 81*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_SPICLK1_4mA (0x1 << 18) 82*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_SPICLK1_7mA (0x2 << 18) 83*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_DRVCON_SPICLK1_9mA (0x3 << 18) 84*c6ff132dSArnd Bergmann 85*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_DQS_PUD_MASK (0x3 << 16) 86*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT (16) 87*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED (0x0 << 16) 88*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN (0x1 << 16) 89*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_DQS_PUD_UP (0x2 << 16) 90*c6ff132dSArnd Bergmann 91*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_D_PUD1_MASK (0x3 << 14) 92*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT (14) 93*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED (0x0 << 14) 94*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_D_PUD1_DOWN (0x1 << 14) 95*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_D_PUD1_UP (0x2 << 14) 96*c6ff132dSArnd Bergmann 97*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_D_PUD0_MASK (0x3 << 12) 98*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT (12) 99*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED (0x0 << 12) 100*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_D_PUD0_DOWN (0x1 << 12) 101*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM1_D_PUD0_UP (0x2 << 12) 102*c6ff132dSArnd Bergmann 103*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM0_D_PUD_MASK (0x3 << 8) 104*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM0_D_PUD_SHIFT (8) 105*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM0_D_PUD_DISABLED (0x0 << 8) 106*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM0_D_PUD_DOWN (0x1 << 8) 107*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_MEM0_D_PUD_UP (0x2 << 8) 108*c6ff132dSArnd Bergmann 109*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_USBH_DMPD (1 << 7) 110*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_USBH_DPPD (1 << 6) 111*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_USBH_PUSW2 (1 << 5) 112*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_USBH_PUSW1 (1 << 4) 113*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_USBH_SUSPND (1 << 3) 114*c6ff132dSArnd Bergmann 115*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_LCD_SEL_MASK (0x3 << 0) 116*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_LCD_SEL_SHIFT (0) 117*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_LCD_SEL_HOST (0x0 << 0) 118*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_LCD_SEL_RGB (0x1 << 0) 119*c6ff132dSArnd Bergmann #define S3C64XX_SPCON_LCD_SEL_606_656 (0x2 << 0) 120*c6ff132dSArnd Bergmann 121*c6ff132dSArnd Bergmann 122*c6ff132dSArnd Bergmann /* External interrupt registers */ 123*c6ff132dSArnd Bergmann 124*c6ff132dSArnd Bergmann #define S3C64XX_EINT12CON S3C64XX_GPIOREG(0x200) 125*c6ff132dSArnd Bergmann #define S3C64XX_EINT34CON S3C64XX_GPIOREG(0x204) 126*c6ff132dSArnd Bergmann #define S3C64XX_EINT56CON S3C64XX_GPIOREG(0x208) 127*c6ff132dSArnd Bergmann #define S3C64XX_EINT78CON S3C64XX_GPIOREG(0x20C) 128*c6ff132dSArnd Bergmann #define S3C64XX_EINT9CON S3C64XX_GPIOREG(0x210) 129*c6ff132dSArnd Bergmann 130*c6ff132dSArnd Bergmann #define S3C64XX_EINT12FLTCON S3C64XX_GPIOREG(0x220) 131*c6ff132dSArnd Bergmann #define S3C64XX_EINT34FLTCON S3C64XX_GPIOREG(0x224) 132*c6ff132dSArnd Bergmann #define S3C64XX_EINT56FLTCON S3C64XX_GPIOREG(0x228) 133*c6ff132dSArnd Bergmann #define S3C64XX_EINT78FLTCON S3C64XX_GPIOREG(0x22C) 134*c6ff132dSArnd Bergmann #define S3C64XX_EINT9FLTCON S3C64XX_GPIOREG(0x230) 135*c6ff132dSArnd Bergmann 136*c6ff132dSArnd Bergmann #define S3C64XX_EINT12MASK S3C64XX_GPIOREG(0x240) 137*c6ff132dSArnd Bergmann #define S3C64XX_EINT34MASK S3C64XX_GPIOREG(0x244) 138*c6ff132dSArnd Bergmann #define S3C64XX_EINT56MASK S3C64XX_GPIOREG(0x248) 139*c6ff132dSArnd Bergmann #define S3C64XX_EINT78MASK S3C64XX_GPIOREG(0x24C) 140*c6ff132dSArnd Bergmann #define S3C64XX_EINT9MASK S3C64XX_GPIOREG(0x250) 141*c6ff132dSArnd Bergmann 142*c6ff132dSArnd Bergmann #define S3C64XX_EINT12PEND S3C64XX_GPIOREG(0x260) 143*c6ff132dSArnd Bergmann #define S3C64XX_EINT34PEND S3C64XX_GPIOREG(0x264) 144*c6ff132dSArnd Bergmann #define S3C64XX_EINT56PEND S3C64XX_GPIOREG(0x268) 145*c6ff132dSArnd Bergmann #define S3C64XX_EINT78PEND S3C64XX_GPIOREG(0x26C) 146*c6ff132dSArnd Bergmann #define S3C64XX_EINT9PEND S3C64XX_GPIOREG(0x270) 147*c6ff132dSArnd Bergmann 148*c6ff132dSArnd Bergmann #define S3C64XX_PRIORITY S3C64XX_GPIOREG(0x280) 149*c6ff132dSArnd Bergmann #define S3C64XX_PRIORITY_ARB(x) (1 << (x)) 150*c6ff132dSArnd Bergmann 151*c6ff132dSArnd Bergmann #define S3C64XX_SERVICE S3C64XX_GPIOREG(0x284) 152*c6ff132dSArnd Bergmann #define S3C64XX_SERVICEPEND S3C64XX_GPIOREG(0x288) 153*c6ff132dSArnd Bergmann 154*c6ff132dSArnd Bergmann #define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900) 155*c6ff132dSArnd Bergmann #define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904) 156*c6ff132dSArnd Bergmann #define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910) 157*c6ff132dSArnd Bergmann #define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914) 158*c6ff132dSArnd Bergmann #define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918) 159*c6ff132dSArnd Bergmann #define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C) 160*c6ff132dSArnd Bergmann 161*c6ff132dSArnd Bergmann #define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920) 162*c6ff132dSArnd Bergmann #define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924) 163*c6ff132dSArnd Bergmann 164*c6ff132dSArnd Bergmann /* GPIO sleep configuration */ 165*c6ff132dSArnd Bergmann 166*c6ff132dSArnd Bergmann #define S3C64XX_SPCONSLP S3C64XX_GPIOREG(0x880) 167*c6ff132dSArnd Bergmann 168*c6ff132dSArnd Bergmann #define S3C64XX_SPCONSLP_TDO_PULLDOWN (1 << 14) 169*c6ff132dSArnd Bergmann #define S3C64XX_SPCONSLP_CKE1INIT (1 << 5) 170*c6ff132dSArnd Bergmann 171*c6ff132dSArnd Bergmann #define S3C64XX_SPCONSLP_RSTOUT_MASK (0x3 << 12) 172*c6ff132dSArnd Bergmann #define S3C64XX_SPCONSLP_RSTOUT_OUT0 (0x0 << 12) 173*c6ff132dSArnd Bergmann #define S3C64XX_SPCONSLP_RSTOUT_OUT1 (0x1 << 12) 174*c6ff132dSArnd Bergmann #define S3C64XX_SPCONSLP_RSTOUT_HIZ (0x2 << 12) 175*c6ff132dSArnd Bergmann 176*c6ff132dSArnd Bergmann #define S3C64XX_SPCONSLP_KPCOL_MASK (0x3 << 0) 177*c6ff132dSArnd Bergmann #define S3C64XX_SPCONSLP_KPCOL_OUT0 (0x0 << 0) 178*c6ff132dSArnd Bergmann #define S3C64XX_SPCONSLP_KPCOL_OUT1 (0x1 << 0) 179*c6ff132dSArnd Bergmann #define S3C64XX_SPCONSLP_KPCOL_INP (0x2 << 0) 180*c6ff132dSArnd Bergmann 181*c6ff132dSArnd Bergmann 182*c6ff132dSArnd Bergmann #define S3C64XX_SLPEN S3C64XX_GPIOREG(0x930) 183*c6ff132dSArnd Bergmann 184*c6ff132dSArnd Bergmann #define S3C64XX_SLPEN_USE_xSLP (1 << 0) 185*c6ff132dSArnd Bergmann #define S3C64XX_SLPEN_CFG_BYSLPEN (1 << 1) 186*c6ff132dSArnd Bergmann 187*c6ff132dSArnd Bergmann #endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */ 188*c6ff132dSArnd Bergmann 189