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/linux/Documentation/devicetree/bindings/pci/
H A Dmarvell,kirkwood-pcie.yaml28 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
36 This range entry translates the '0x82000000 0 r' PCI address into the
37 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part of the internal
38 register window (as identified by MBUS_ID(0xf0, 0x01)).
42 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
132 bus-range = <0x00 0xff>;
136 … <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
137 … 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
138 … 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
139 … 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dmarvell,mvebu-sata-phy.yaml28 const: 0
43 reg = <0x84000 0x0334>;
46 #phy-cells = <0>;
/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-mv78260.dtsi27 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
34 clocks = <&cpuclk 0>;
49 * MV78260 has 3 PCIe units Gen2.0: Two units can be
62 bus-range = <0x00 0xff>;
65 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
66 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
67 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
H A Darmada-xp-mv78460.dtsi28 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
35 clocks = <&cpuclk 0>;
66 * MV78460 has 4 PCIe units Gen2.0: Two units can be
79 bus-range = <0x00 0xff>;
82 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
83 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
84 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
85 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
H A Dkirkwood.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
37 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */
38 MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */
39 MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */
42 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
43 pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
48 cle = <0>;
52 reg = <MBUS_ID(0x01, 0x2f) 0 0x400>;
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dqoriq-fman3-0.dtsi14 cell-index = <0>;
16 ranges = <0x0 0x0 0x1a00000 0xfe000>;
17 reg = <0x0 0x1a00000 0x0 0xfe000>;
20 clocks = <&clockgen QORIQ_CLK_FMAN 0>;
22 fsl,qman-channel-range = <0x800 0x10>;
26 muram@0 {
28 reg = <0x0 0x60000>;
32 cell-index = <0x2>;
34 reg = <0x82000 0x1000>;
38 cell-index = <0x3>;
[all …]
/linux/arch/arm/mach-mv78xx0/
H A Dmv78xx0.h17 * f0800000 PCIe #0 I/O space
29 * fee00000 f0800000 64K PCIe #0 I/O space
39 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
40 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
41 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
42 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
45 #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
48 #define MV78XX0_REGS_PHYS_BASE 0xf1000000
49 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
52 #define MV78XX0_SRAM_PHYS_BASE (0xf2200000)
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-fman3-1.dtsi2 * QorIQ FMan v3 device tree stub [ controller @ offset 0x500000 ]
40 ranges = <0 0x500000 0xfe000>;
41 reg = <0x500000 0xfe000>;
42 interrupts = <97 2 0 0>, <16 2 1 0>;
45 fsl,qman-channel-range = <0x820 0x10>;
48 muram@0 {
50 reg = <0x0 0x60000>;
54 cell-index = <0x2>;
56 reg = <0x82000 0x1000>;
60 cell-index = <0x3>;
[all …]
H A Dqoriq-fman-0.dtsi2 * QorIQ FMan device tree stub [ controller @ offset 0x400000 ]
38 cell-index = <0>;
40 ranges = <0 0x400000 0xfe000>;
41 reg = <0x400000 0xfe000>;
42 interrupts = <96 2 0 0>, <16 2 1 1>;
43 clocks = <&clockgen 3 0>;
45 fsl,qman-channel-range = <0x40 0xc>;
48 muram@0 {
50 reg = <0x0 0x28000>;
54 cell-index = <0x1>;
[all …]
H A Dqoriq-fman-1.dtsi2 * QorIQ FMan device tree stub [ controller @ offset 0x500000 ]
40 ranges = <0 0x500000 0xfe000>;
41 reg = <0x500000 0xfe000>;
42 interrupts = <97 2 0 0>, <16 2 1 0>;
45 fsl,qman-channel-range = <0x60 0xc>;
48 muram@0 {
50 reg = <0x0 0x28000>;
54 cell-index = <0x1>;
56 reg = <0x81000 0x1000>;
60 cell-index = <0x2>;
[all …]
H A Dqoriq-fman3l-0.dtsi2 * QorIQ FMan v3 device tree stub [ controller @ offset 0x400000 ]
38 cell-index = <0>;
40 ranges = <0 0x400000 0xfe000>;
41 reg = <0x400000 0xfe000>;
42 interrupts = <96 2 0 0>, <16 2 1 1>;
43 clocks = <&clockgen 3 0>;
45 fsl,qman-channel-range = <0x800 0x10>;
48 muram@0 {
50 reg = <0x0 0x30000>;
54 cell-index = <0x2>;
[all …]
H A Dqoriq-fman3-0.dtsi2 * QorIQ FMan v3 device tree stub [ controller @ offset 0x400000 ]
38 cell-index = <0>;
40 ranges = <0 0x400000 0xfe000>;
41 reg = <0x400000 0xfe000>;
42 interrupts = <96 2 0 0>, <16 2 1 1>;
43 clocks = <&clockgen 3 0>;
45 fsl,qman-channel-range = <0x800 0x10>;
48 muram@0 {
50 reg = <0x0 0x60000>;
54 cell-index = <0x2>;
[all …]
H A Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
/linux/arch/arm/mach-imx/
H A Dmx3x.h36 #define MX3x_L2CC_BASE_ADDR 0x30000000
42 #define MX3x_AIPS1_BASE_ADDR 0x43f00000
44 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
45 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
46 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
47 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
48 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
49 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
50 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
51 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
[all …]
/linux/arch/arm64/boot/dts/apple/
H A Ds800-0-3.dtsi22 #clock-cells = <0>;
29 #size-cells = <0>;
31 cpu0: cpu@0 {
33 reg = <0x0 0x0>;
34 cpu-release-addr = <0 0>; /* To be filled in by loader */
40 i-cache-size = <0x10000>;
41 d-cache-size = <0x10000>;
46 reg = <0x0 0x1>;
47 cpu-release-addr = <0 0>; /* To be filled in by loader */
53 i-cache-size = <0x10000>;
[all …]
H A Ds8001.dtsi22 #clock-cells = <0>;
29 #size-cells = <0>;
31 cpu0: cpu@0 {
33 reg = <0x0 0x0>;
34 cpu-release-addr = <0 0>; /* To be filled in by loader */
40 i-cache-size = <0x10000>;
41 d-cache-size = <0x10000>;
46 reg = <0x0 0x1>;
47 cpu-release-addr = <0 0>; /* To be filled in by loader */
53 i-cache-size = <0x10000>;
[all …]
H A Dt8011.dtsi22 #clock-cells = <0>;
29 #size-cells = <0>;
31 cpu0: cpu@0 {
33 reg = <0x0 0x0>;
34 cpu-release-addr = <0 0>; /* To be filled by loader */
40 i-cache-size = <0x10000>; /* P-core */
41 d-cache-size = <0x10000>; /* P-core */
46 reg = <0x0 0x1>;
47 cpu-release-addr = <0 0>; /* To be filled by loader */
53 i-cache-size = <0x10000>; /* P-core */
[all …]
H A Dt8010.dtsi22 #clock-cells = <0>;
29 #size-cells = <0>;
31 cpu0: cpu@0 {
33 reg = <0x0 0x0>;
34 cpu-release-addr = <0 0>; /* To be filled by loader */
40 i-cache-size = <0x10000>; /* P-core */
41 d-cache-size = <0x10000>; /* P-core */
46 reg = <0x0 0x1>;
47 cpu-release-addr = <0 0>; /* To be filled by loader */
53 i-cache-size = <0x10000>; /* P-core */
[all …]
H A Dt8012.dtsi22 #clock-cells = <0>;
29 #size-cells = <0>;
33 reg = <0x0 0x10000>;
34 cpu-release-addr = <0 0>; /* To be filled by loader */
40 i-cache-size = <0x10000>; /* P-core */
41 d-cache-size = <0x10000>; /* P-core */
46 reg = <0x0 0x10001>;
47 cpu-release-addr = <0 0>; /* To be filled by loader */
53 i-cache-size = <0x10000>; /* P-core */
54 d-cache-size = <0x10000>; /* P-core */
[all …]
H A Dt8015.dtsi22 #clock-cells = <0>;
29 #size-cells = <0>;
57 cpu_e0: cpu@0 {
59 reg = <0x0 0x0>;
60 cpu-release-addr = <0 0>; /* To be filled by loader */
67 i-cache-size = <0x8000>;
68 d-cache-size = <0x8000>;
73 reg = <0x0 0x1>;
74 cpu-release-addr = <0 0>; /* To be filled by loader */
81 i-cache-size = <0x8000>;
[all …]
H A Dt8011-pmgr.dtsi11 reg = <0x80000 4>;
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
20 reg = <0x80008 4>;
21 #power-domain-cells = <0>;
22 #reset-cells = <0>;
29 reg = <0x80010 4>;
30 #power-domain-cells = <0>;
31 #reset-cells = <0>;
38 reg = <0x80040 4>;
[all …]
/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zc1751-xm016-dc2.dts38 memory@0 {
40 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
47 pinctrl-0 = <&pinctrl_can0_default>;
53 pinctrl-0 = <&pinctrl_can1_default>;
93 pinctrl-0 = <&pinctrl_gem2_default>;
96 #size-cells = <0>;
99 ti,rx-internal-delay = <0x8>;
100 ti,tx-internal-delay = <0xa>;
101 ti,fifo-depth = <0x1>;
115 pinctrl-0 = <&pinctrl_i2c0_default>;
[all …]
/linux/drivers/pinctrl/qcom/
H A Dpinctrl-qcm2290.c12 #define REG_SIZE 0x1000
33 .io_reg = 0x4 + REG_SIZE * id, \
34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
35 .intr_status_reg = 0xc + REG_SIZE * id, \
36 .intr_target_reg = 0x8 + REG_SIZE * id, \
38 .pull_bit = 0, \
43 .in_bit = 0, \
45 .intr_enable_bit = 0, \
46 .intr_status_bit = 0, \
61 .io_reg = 0, \
[all …]
/linux/drivers/soc/tegra/cbb/
H A Dtegra234-cbb.c8 * Error types supported by CBB2.0 are:
27 #define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0
28 #define FABRIC_EN_CFG_STATUS_0_0 0x40
29 #define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60
30 #define FABRIC_EN_CFG_ADDR_LOW_0 0x80
31 #define FABRIC_EN_CFG_ADDR_HI_0 0x84
33 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_INDEX_0_0 0x100
34 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_LOW_0 0x140
35 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_HI_0 0x144
37 #define FABRIC_MN_INITIATOR_ERR_EN_0 0x200
[all …]
/linux/drivers/pci/controller/
H A Dpcie-apple.c37 #define CORE_RC_PHYIF_CTL 0x00024
38 #define CORE_RC_PHYIF_CTL_RUN BIT(0)
39 #define CORE_RC_PHYIF_STAT 0x00028
41 #define CORE_RC_CTL 0x00050
42 #define CORE_RC_CTL_RUN BIT(0)
43 #define CORE_RC_STAT 0x00058
44 #define CORE_RC_STAT_READY BIT(0)
45 #define CORE_FABRIC_STAT 0x04000
46 #define CORE_FABRIC_STAT_MASK 0x001F001F
48 #define CORE_PHY_DEFAULT_BASE(port) (0x84000 + 0x4000 * (port))
[all …]

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