Lines Matching +full:0 +full:x84000

22 		#clock-cells = <0>;
29 		#size-cells = <0>;
57 		cpu_e0: cpu@0 {
59 			reg = <0x0 0x0>;
60 			cpu-release-addr = <0 0>; /* To be filled by loader */
67 			i-cache-size = <0x8000>;
68 			d-cache-size = <0x8000>;
73 			reg = <0x0 0x1>;
74 			cpu-release-addr = <0 0>; /* To be filled by loader */
81 			i-cache-size = <0x8000>;
82 			d-cache-size = <0x8000>;
87 			reg = <0x0 0x2>;
88 			cpu-release-addr = <0 0>; /* To be filled by loader */
95 			i-cache-size = <0x8000>;
96 			d-cache-size = <0x8000>;
101 			reg = <0x0 0x3>;
102 			cpu-release-addr = <0 0>; /* To be filled by loader */
109 			i-cache-size = <0x8000>;
110 			d-cache-size = <0x8000>;
115 			reg = <0x0 0x10004>;
116 			cpu-release-addr = <0 0>; /* To be filled by loader */
123 			i-cache-size = <0x10000>;
124 			d-cache-size = <0x10000>;
129 			reg = <0x0 0x10005>;
130 			cpu-release-addr = <0 0>; /* To be filled by loader */
137 			i-cache-size = <0x10000>;
138 			d-cache-size = <0x10000>;
141 		l2_cache_0: l2-cache-0 {
145 			cache-size = <0x100000>;
152 			cache-size = <0x800000>;
156 	mistral_opp: opp-table-0 {
189 #if 0
238 #if 0
258 			reg = <0x2 0x08e20000 0 0x1000>;
259 			#performance-domain-cells = <0>;
264 			reg = <0x2 0x08ea0000 0 0x1000>;
265 			#performance-domain-cells = <0>;
270 			reg = <0x2 0x2e600000 0x0 0x4000>;
283 			reg = <0x2 0x32100000 0x0 0x8000>;
294 			reg = <0x2 0x32000000 0 0x8c000>;
299 			reg = <0x2 0x32200080 0x0 0x8>;
306 			reg = <0x2 0x33100000 0x0 0x1000>;
311 			gpio-ranges = <&pinctrl_ap 0 0 223>;
328 			reg = <0x2 0x340f0000 0x0 0x4000>;
332 			gpio-ranges = <&pinctrl_aop 0 0 49>;
349 			reg = <0x2 0x351f0000 0x0 0x4000>;
353 			gpio-ranges = <&pinctrl_nub 0 0 8>;
369 			reg = <0x2 0x35200000 0 0x84000>;
374 			reg = <0x2 0x352b0000 0x0 0x4000>;
382 			reg = <0x2 0x36024000 0x0 0x4000>;
386 			gpio-ranges = <&pinctrl_smc 0 0 6>;