37 #define CORE_RC_PHYIF_CTL		0x00024
38 #define   CORE_RC_PHYIF_CTL_RUN		BIT(0)
39 #define CORE_RC_PHYIF_STAT		0x00028
41 #define CORE_RC_CTL			0x00050
42 #define   CORE_RC_CTL_RUN		BIT(0)
43 #define CORE_RC_STAT			0x00058
44 #define   CORE_RC_STAT_READY		BIT(0)
45 #define CORE_FABRIC_STAT		0x04000
46 #define   CORE_FABRIC_STAT_MASK		0x001F001F
48 #define CORE_PHY_DEFAULT_BASE(port)	(0x84000 + 0x4000 * (port))
50 #define PHY_LANE_CFG			0x00000
51 #define   PHY_LANE_CFG_REFCLK0REQ	BIT(0)
57 #define PHY_LANE_CTL			0x00004
60 #define PORT_LTSSMCTL			0x00080
61 #define   PORT_LTSSMCTL_START		BIT(0)
62 #define PORT_INTSTAT			0x00100
78 #define PORT_INTMSK			0x00104
79 #define PORT_INTMSKSET			0x00108
80 #define PORT_INTMSKCLR			0x0010c
81 #define PORT_MSICFG			0x00124
82 #define   PORT_MSICFG_EN		BIT(0)
84 #define PORT_MSIBASE			0x00128
86 #define PORT_MSIADDR			0x00168
87 #define PORT_LINKSTS			0x00208
88 #define   PORT_LINKSTS_UP		BIT(0)
90 #define PORT_LINKCMDSTS			0x00210
91 #define PORT_OUTS_NPREQS		0x00284
94 #define PORT_RXWR_FIFO			0x00288
96 #define   PORT_RXWR_FIFO_DATA		GENMASK(9, 0)
97 #define PORT_RXRD_FIFO			0x0028C
98 #define   PORT_RXRD_FIFO_REQ		GENMASK(6, 0)
99 #define PORT_OUTS_CPLS			0x00290
101 #define   PORT_OUTS_CPLS_WAIT		GENMASK(6, 0)
102 #define PORT_APPCLK			0x00800
103 #define   PORT_APPCLK_EN		BIT(0)
105 #define PORT_STATUS			0x00804
106 #define   PORT_STATUS_READY		BIT(0)
107 #define PORT_REFCLK			0x00810
108 #define   PORT_REFCLK_EN		BIT(0)
110 #define PORT_PERST			0x00814
111 #define   PORT_PERST_OFF		BIT(0)
112 #define PORT_RID2SID			0x00828
117 #define   PORT_RID2SID_FUNC_SHIFT	0
118 #define PORT_OUTS_PREQS_HDR		0x00980
119 #define   PORT_OUTS_PREQS_HDR_MASK	GENMASK(9, 0)
120 #define PORT_OUTS_PREQS_DATA		0x00984
121 #define   PORT_OUTS_PREQS_DATA_MASK	GENMASK(15, 0)
122 #define PORT_TUNCTRL			0x00988
123 #define   PORT_TUNCTRL_PERST_ON		BIT(0)
125 #define PORT_TUNSTAT			0x0098c
126 #define   PORT_TUNSTAT_PERST_ON		BIT(0)
128 #define PORT_PREFMEM_ENABLE		0x00994
131 #define PORT_T602X_MSIADDR	0x016c
132 #define PORT_T602X_MSIADDR_HI	0x0170
133 #define PORT_T602X_PERST	0x082c
134 #define PORT_T602X_RID2SID	0x3000
135 #define PORT_T602X_MSIMAP	0x3800
138 #define PORT_MSIMAP_TARGET	GENMASK(7, 0)
141  * The doorbell address is set to 0xfffff000, which by convention
163 	.port_msiaddr_hi	= 0,
167 	.port_msimap		= 0,
172 	.phy_lane_ctl		= 0,
175 	.port_refclk		= 0,
254 	if (hwirq < 0)  in apple_msi_domain_alloc()
263 	for (i = 0; i < nr_irqs; i++) {  in apple_msi_domain_alloc()
268 	return 0;  in apple_msi_domain_alloc()
329 	return 0;  in apple_port_irq_set_type()
348 	for (i = 0; i < nr_irqs; i++) {  in apple_port_irq_domain_alloc()
352 		if (hwirq_is_intx(fwspec->param[0] + i)) {  in apple_port_irq_domain_alloc()
357 		irq_domain_set_info(domain, virq + i, fwspec->param[0] + i,  in apple_port_irq_domain_alloc()
364 	return 0;  in apple_port_irq_domain_alloc()
372 	for (i = 0; i < nr_irqs; i++) {  in apple_port_irq_domain_free()
408 	u32 val = 0;  in apple_pcie_port_setup_irq()
423 	writel_relaxed(~0, port->base + PORT_INTMSK);  in apple_pcie_port_setup_irq()
424 	writel_relaxed(~0, port->base + PORT_INTSTAT);  in apple_pcie_port_setup_irq()
425 	writel_relaxed(~0, port->base + PORT_LINKCMDSTS);  in apple_pcie_port_setup_irq()
434 		writel_relaxed(0, port->base + pcie->hw->port_msiaddr_hi);  in apple_pcie_port_setup_irq()
438 		for (int i = 0; i < pcie->nvecs; i++)  in apple_pcie_port_setup_irq()
443 		writel_relaxed(0, port->base + PORT_MSIBASE);  in apple_pcie_port_setup_irq()
448 	return 0;  in apple_pcie_port_setup_irq()
484 	for (i = 0; i < ARRAY_SIZE(port_irqs); i++) {  in apple_pcie_port_register_irqs()
489 				[0]	= port_irqs[i].hwirq,  in apple_pcie_port_register_irqs()
500 		ret = request_irq(irq, apple_pcie_port_irq, 0,  in apple_pcie_port_register_irqs()
505 	return 0;  in apple_pcie_port_register_irqs()
522 	if (res < 0)  in apple_pcie_setup_refclk()
530 	if (res < 0)  in apple_pcie_setup_refclk()
541 	return 0;  in apple_pcie_setup_refclk()
581 	ret = of_property_read_u32_index(np, "reg", 0, &idx);  in apple_pcie_setup_port()
614 	if (ret < 0)  in apple_pcie_setup_port()
617 	/* The minimal Tperst-clk value is 100us (PCIe CEM r5.0, 2.9.2) */  in apple_pcie_setup_port()
622 	gpiod_set_value_cansleep(reset, 0);  in apple_pcie_setup_port()
624 	/* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */  in apple_pcie_setup_port()
629 	if (ret < 0) {  in apple_pcie_setup_port()
646 	for (i = 0; i < pcie->hw->max_rid2sid; i++) {  in apple_pcie_setup_port()
647 		if (apple_pcie_rid2sid_write(port, i, 0xbad1d) != 0xbad1d)  in apple_pcie_setup_port()
649 		apple_pcie_rid2sid_write(port, i, 0);  in apple_pcie_setup_port()
670 	return 0;  in apple_pcie_setup_port()
698 					 "#interrupt-cells", 0, &args);  in apple_msi_init()
724 	return 0;  in apple_msi_init()
789 		return 0;  in apple_pcie_enable_device()
801 	idx = bitmap_find_free_region(port->sid_map, port->sid_map_sz, 0);  in apple_pcie_enable_device()
802 	if (idx >= 0) {  in apple_pcie_enable_device()
813 	return idx >= 0 ? 0 : -ENOSPC;  in apple_pcie_enable_device()
832 		if ((val & 0xffff) == rid) {  in apple_pcie_disable_device()
833 			apple_pcie_rid2sid_write(port, idx, 0);  in apple_pcie_disable_device()
834 			bitmap_release_region(port->sid_map, idx, 0);  in apple_pcie_disable_device()
861 	return 0;  in apple_pcie_init()