Lines Matching +full:0 +full:x84000
12 #define REG_SIZE 0x1000
33 .io_reg = 0x4 + REG_SIZE * id, \
34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
35 .intr_status_reg = 0xc + REG_SIZE * id, \
36 .intr_target_reg = 0x8 + REG_SIZE * id, \
38 .pull_bit = 0, \
43 .in_bit = 0, \
45 .intr_enable_bit = 0, \
46 .intr_status_bit = 0, \
61 .io_reg = 0, \
62 .intr_cfg_reg = 0, \
63 .intr_status_reg = 0, \
64 .intr_target_reg = 0, \
86 .io_reg = offset + 0x4, \
87 .intr_cfg_reg = 0, \
88 .intr_status_reg = 0, \
89 .intr_target_reg = 0, \
92 .drv_bit = 0, \
95 .out_bit = 0, \
105 PINCTRL_PIN(0, "GPIO_0"),
243 DECLARE_MSM_GPIO_PINS(0);
962 [0] = PINGROUP(0, qup0, m_voc, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _),
1089 [127] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x84004, 0, 0),
1090 [128] = SDC_QDSD_PINGROUP(sdc1_clk, 0x84000, 13, 6),
1091 [129] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x84000, 11, 3),
1092 [130] = SDC_QDSD_PINGROUP(sdc1_data, 0x84000, 9, 0),
1093 [131] = SDC_QDSD_PINGROUP(sdc2_clk, 0x86000, 14, 6),
1094 [132] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x86000, 11, 3),
1095 [133] = SDC_QDSD_PINGROUP(sdc2_data, 0x86000, 9, 0),
1099 { 0, 84 }, { 3, 75 }, { 4, 16 }, { 6, 59 }, { 8, 63 }, { 11, 17 },