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/linux/Documentation/i2c/busses/
H A Dscx200_acb.rst15 By default the driver uses two base addresses 0x820 and 0x840.
16 If you want only one base address, specify the second as 0 so as to
28 The SC1100 WRAP boards are known to use base addresses 0x810 and 0x820.
32 scx200_acb.base=0x810,0x820
37 options scx200_acb base=0x810,0x820
/linux/drivers/media/i2c/cx25840/
H A Dcx25840-audio.c39 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in cx25840_set_audclk_freq()
40 * AUX_PLL Integer = 0x06, AUX PLL Post Divider = 0x10 in cx25840_set_audclk_freq()
42 cx25840_write4(client, 0x108, 0x1006040f); in cx25840_set_audclk_freq()
45 * VID_PLL Fraction (register 0x10c) = 0x2be2fe in cx25840_set_audclk_freq()
46 * 28636360 * 0xf.15f17f0/4 = 108 MHz in cx25840_set_audclk_freq()
51 * AUX_PLL Fraction = 0x1bb39ee in cx25840_set_audclk_freq()
52 * 28636363 * 0x6.dd9cf70/0x10 = 32000 * 384 in cx25840_set_audclk_freq()
57 cx25840_write4(client, 0x110, 0x01bb39ee); in cx25840_set_audclk_freq()
61 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider in cx25840_set_audclk_freq()
63 cx25840_write(client, 0x127, 0x50); in cx25840_set_audclk_freq()
[all …]
/linux/arch/m68k/include/asm/
H A Dmac_asc.h13 #define ASC_BUF_BASE 0x00 /* RAM buffer offset */
14 #define ASC_BUF_SIZE 0x800
16 #define ASC_CONTROL 0x800
17 #define ASC_CONTROL_OFF 0x00
18 #define ASC_FREQ(chan,byte) ((0x810)+((chan)<<3)+(byte))
19 #define ASC_ENABLE 0x801
20 #define ASC_ENABLE_SAMPLE 0x02
21 #define ASC_MODE 0x802
22 #define ASC_MODE_SAMPLE 0x02
24 #define ASC_VOLUME 0x806
[all …]
/linux/drivers/net/ethernet/freescale/dpaa2/
H A Ddprtc-cmd.h19 #define DPRTC_CMDID_CLOSE DPRTC_CMD(0x800)
20 #define DPRTC_CMDID_OPEN DPRTC_CMD(0x810)
22 #define DPRTC_CMDID_SET_IRQ_ENABLE DPRTC_CMD(0x012)
23 #define DPRTC_CMDID_GET_IRQ_ENABLE DPRTC_CMD(0x013)
24 #define DPRTC_CMDID_SET_IRQ_MASK DPRTC_CMD_V2(0x014)
25 #define DPRTC_CMDID_GET_IRQ_MASK DPRTC_CMD(0x015)
26 #define DPRTC_CMDID_GET_IRQ_STATUS DPRTC_CMD(0x016)
27 #define DPRTC_CMDID_CLEAR_IRQ_STATUS DPRTC_CMD(0x017)
/linux/drivers/clk/sophgo/
H A Dclk-cv1800.h14 #define REG_PLL_G2_CTRL 0x800
15 #define REG_PLL_G2_STATUS 0x804
16 #define REG_MIPIMPLL_CSR 0x808
17 #define REG_A0PLL_CSR 0x80C
18 #define REG_DISPPLL_CSR 0x810
19 #define REG_CAM0PLL_CSR 0x814
20 #define REG_CAM1PLL_CSR 0x818
21 #define REG_PLL_G2_SSC_SYN_CTRL 0x840
22 #define REG_A0PLL_SSC_SYN_CTRL 0x850
23 #define REG_A0PLL_SSC_SYN_SET 0x854
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/linux/drivers/net/ethernet/broadcom/
H A Dbcm4908_enet.h5 #define ENET_CONTROL 0x000
6 #define ENET_MIB_CTRL 0x004
7 #define ENET_MIB_CTRL_CLR_MIB 0x00000001
8 #define ENET_RX_ERR_MASK 0x008
9 #define ENET_MIB_MAX_PKT_SIZE 0x00C
10 #define ENET_MIB_MAX_PKT_SIZE_VAL 0x00003fff
11 #define ENET_DIAG_OUT 0x01c
12 #define ENET_ENABLE_DROP_PKT 0x020
13 #define ENET_IRQ_ENABLE 0x024
14 #define ENET_IRQ_ENABLE_OVFL 0x00000001
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/linux/arch/arm/mach-s3c/
H A Dregs-syscon-power-s3c64xx.h14 #define S3C64XX_PWR_CFG S3C_SYSREG(0x804)
28 #define S3C64XX_PWRCFG_CFG_WFI_MASK (0x3 << 5)
30 #define S3C64XX_PWRCFG_CFG_WFI_IGNORE (0x0 << 5)
31 #define S3C64XX_PWRCFG_CFG_WFI_IDLE (0x1 << 5)
32 #define S3C64XX_PWRCFG_CFG_WFI_STOP (0x2 << 5)
33 #define S3C64XX_PWRCFG_CFG_WFI_SLEEP (0x3 << 5)
35 #define S3C64XX_PWRCFG_CFG_BATFLT_MASK (0x3 << 3)
37 #define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE (0x0 << 3)
38 #define S3C64XX_PWRCFG_CFG_BATFLT_IRQ (0x1 << 3)
39 #define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP (0x3 << 3)
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/linux/include/dt-bindings/pinctrl/
H A Dam33xx.h18 #define SLEWCTRL_FAST 0
30 #define PIN_OUTPUT_PULLDOWN 0
43 #define AM335X_PIN_OFFSET_MIN 0x0800U
45 #define AM335X_PIN_GPMC_AD0 0x800
46 #define AM335X_PIN_GPMC_AD1 0x804
47 #define AM335X_PIN_GPMC_AD2 0x808
48 #define AM335X_PIN_GPMC_AD3 0x80c
49 #define AM335X_PIN_GPMC_AD4 0x810
50 #define AM335X_PIN_GPMC_AD5 0x814
51 #define AM335X_PIN_GPMC_AD6 0x818
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/linux/include/linux/usb/
H A Dusb338x.h19 #define SCRATCH 0x0b
36 #define USB3380_EP_CFG_MASK_IN ((0x3 << IN_ENDPOINT_TYPE) | \
38 #define USB3380_EP_CFG_MASK_OUT ((0x3 << OUT_ENDPOINT_TYPE) | \
45 #define DEVICE_CLASS 0
48 #define U1_SYSTEM_EXIT_LATENCY 0
51 #define U1_DEVICE_EXIT_LATENCY 0
55 #define USB_L1_LPM_SUPPORT 0
58 #define BEST_EFFORT_LATENCY_TOLERANCE 0
66 #define SERIAL_NUMBER_STRING_ENABLE 0
79 #define GPEP0_TIMEOUT_ENABLE 0
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/linux/drivers/net/ethernet/ezchip/
H A Dnps_enet.h10 #define NPS_ENET_NAPI_POLL_WEIGHT 0x2
11 #define NPS_ENET_MAX_FRAME_LENGTH 0x3FFF
12 #define NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR 0x7
13 #define NPS_ENET_GE_MAC_CFG_0_RX_IFG 0x5
14 #define NPS_ENET_GE_MAC_CFG_0_TX_IFG 0xC
15 #define NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN 0x7
16 #define NPS_ENET_GE_MAC_CFG_2_STAT_EN 0x3
17 #define NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH 0x14
18 #define NPS_ENET_GE_MAC_CFG_3_MAX_LEN 0x3FFC
20 #define NPS_ENET_DISABLE 0
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/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_ht.h8 #define B43_PHY_HT_BBCFG 0x001 /* BB config */
9 #define B43_PHY_HT_BBCFG_RSTCCA 0x4000 /* Reset CCA */
10 #define B43_PHY_HT_BBCFG_RSTRX 0x8000 /* Reset RX */
11 #define B43_PHY_HT_BANDCTL 0x009 /* Band control */
12 #define B43_PHY_HT_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
13 #define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */
14 #define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */
15 #define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */
16 #define B43_PHY_HT_CLASS_CTL 0x0B0 /* Classifier control */
17 #define B43_PHY_HT_CLASS_CTL_CCK_EN 0x0001 /* CCK enable */
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/linux/arch/powerpc/include/asm/
H A Dxive-regs.h29 * store at 0 and some ESBs support doing a trigger via a
32 #define XIVE_ESB_STORE_EOI 0x400 /* Store */
33 #define XIVE_ESB_LOAD_EOI 0x000 /* Load */
34 #define XIVE_ESB_GET 0x800 /* Load */
35 #define XIVE_ESB_SET_PQ_00 0xc00 /* Load */
36 #define XIVE_ESB_SET_PQ_01 0xd00 /* Load */
37 #define XIVE_ESB_SET_PQ_10 0xe00 /* Load */
38 #define XIVE_ESB_SET_PQ_11 0xf00 /* Load */
46 #define XIVE_ESB_LD_ST_MO 0x40 /* Load-after-store ordering */
48 #define XIVE_ESB_VAL_P 0x2
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H A Dpasemi_dma.h13 /* status register layout in IOB region, at 0xfb800000 */
24 PAS_DMA_CAP_TXCH = 0x44, /* Transmit Channel Info */
25 PAS_DMA_CAP_RXCH = 0x48, /* Transmit Channel Info */
26 PAS_DMA_CAP_IFI = 0x4c, /* Interface Info */
27 PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */
28 PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */
29 PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */
30 PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */
31 PAS_DMA_COM_CFG = 0x114, /* Common config reg */
32 PAS_DMA_TXF_SFLG0 = 0x140, /* Set flags */
[all …]
/linux/drivers/reset/hisilicon/
H A Dhi6220_reset.c22 #define PERIPH_ASSERT_OFFSET 0x300
23 #define PERIPH_DEASSERT_OFFSET 0x304
24 #define PERIPH_MAX_INDEX 0x509
26 #define SC_MEDIA_RSTEN 0x052C
27 #define SC_MEDIA_RSTDIS 0x0530
49 u32 offset = idx & 0xff; in hi6220_peripheral_assert()
50 u32 reg = PERIPH_ASSERT_OFFSET + bank * 0x10; in hi6220_peripheral_assert()
61 u32 offset = idx & 0xff; in hi6220_peripheral_deassert()
62 u32 reg = PERIPH_DEASSERT_OFFSET + bank * 0x10; in hi6220_peripheral_deassert()
95 #define AO_SCTRL_SC_PW_CLKEN0 0x800
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/linux/drivers/hsi/controllers/
H A Domap_ssi_regs.h15 #define SSI_REVISION_REG 0
16 # define SSI_REV_MAJOR 0xf0
17 # define SSI_REV_MINOR 0xf
18 #define SSI_SYSCONFIG_REG 0x10
19 # define SSI_AUTOIDLE (1 << 0)
21 # define SSI_SIDLEMODE_FORCE 0
24 # define SSI_SIDLEMODE_MASK 0x18
25 # define SSI_MIDLEMODE_FORCE 0
28 # define SSI_MIDLEMODE_MASK 0x3000
29 #define SSI_SYSSTATUS_REG 0x14
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/linux/drivers/dma/
H A Dst_fdma.h63 #define FDMA_NODE_CTRL_REQ_MAP_MASK GENMASK(4, 0)
64 #define FDMA_NODE_CTRL_REQ_MAP_FREE_RUN 0x0
150 #define FDMA_CMD_STA_OFST 0xFC0
151 #define FDMA_CMD_SET_OFST 0xFC4
152 #define FDMA_CMD_CLR_OFST 0xFC8
153 #define FDMA_CMD_MASK_OFST 0xFCC
154 #define FDMA_CMD_START(ch) (0x1 << (ch << 1))
155 #define FDMA_CMD_PAUSE(ch) (0x2 << (ch << 1))
156 #define FDMA_CMD_FLUSH(ch) (0x3 << (ch << 1))
158 #define FDMA_INT_STA_OFST 0xFD0
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/linux/drivers/phy/ralink/
H A Dphy-ralink-usb.c22 #define RT_SYSC_REG_SYSCFG1 0x014
23 #define RT_SYSC_REG_CLKCFG1 0x030
24 #define RT_SYSC_REG_USB_PHY_CFG 0x05c
26 #define OFS_U2_PHY_AC0 0x800
27 #define OFS_U2_PHY_AC1 0x804
28 #define OFS_U2_PHY_AC2 0x808
29 #define OFS_U2_PHY_ACR0 0x810
30 #define OFS_U2_PHY_ACR1 0x814
31 #define OFS_U2_PHY_ACR2 0x818
32 #define OFS_U2_PHY_ACR3 0x81C
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/linux/arch/alpha/kernel/
H A Dsys_eiger.c46 mask = (irq >= 64 ? mask << 16 : mask >> ((irq - 16) & 0x30)); in eiger_update_irq_hw()
47 regaddr = 0x510 + (((irq - 16) >> 2) & 0x0c); in eiger_update_irq_hw()
48 outl(mask & 0xffff0000UL, regaddr); in eiger_update_irq_hw()
82 * The PALcode will have passed us vectors 0x800 or 0x810, in eiger_device_interrupt()
97 intstatus = inw(0x500) & 15; in eiger_device_interrupt()
107 if (intstatus & 1) handle_irq(16+0); in eiger_device_interrupt()
116 int irq = (vector - 0x800) >> 4; in eiger_srm_device_interrupt()
125 outb(0, DMA1_RESET_REG); in eiger_init_irq()
126 outb(0, DMA2_RESET_REG); in eiger_init_irq()
128 outb(0, DMA2_MASK_REG); in eiger_init_irq()
[all …]
H A Dsys_takara.c41 mask = (irq >= 64 ? mask << 16 : mask >> ((irq - 16) & 0x30)); in takara_update_irq_hw()
42 regaddr = 0x510 + (((irq - 16) >> 2) & 0x0c); in takara_update_irq_hw()
43 outl(mask & 0xffff0000UL, regaddr); in takara_update_irq_hw()
77 * The PALcode will have passed us vectors 0x800 or 0x810, in takara_device_interrupt()
92 intstatus = inw(0x500) & 15; in takara_device_interrupt()
102 if (intstatus & 1) handle_irq(16+0); in takara_device_interrupt()
111 int irq = (vector - 0x800) >> 4; in takara_srm_device_interrupt()
125 unsigned int ctlreg = inl(0x500); in takara_init_irq()
128 ctlreg &= ~0x8000; in takara_init_irq()
129 outl(ctlreg, 0x500); in takara_init_irq()
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_backend.h20 #define SUN4I_BACKEND_MODCTL_REG 0x800
24 #define SUN4I_BACKEND_MODCTL_OUT_LCD0 (0 << 20)
34 #define SUN4I_BACKEND_MODCTL_DEBE_EN BIT(0)
36 #define SUN4I_BACKEND_BACKCOLOR_REG 0x804
39 #define SUN4I_BACKEND_DISSIZE_REG 0x808
40 #define SUN4I_BACKEND_DISSIZE(w, h) (((((h) - 1) & 0xffff) << 16) | \
41 (((w) - 1) & 0xffff))
43 #define SUN4I_BACKEND_LAYSIZE_REG(l) (0x810 + (0x4 * (l)))
44 #define SUN4I_BACKEND_LAYSIZE(w, h) (((((h) - 1) & 0x1fff) << 16) | \
45 (((w) - 1) & 0x1fff))
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/linux/arch/arm/boot/dts/ti/omap/
H A Dam437x-gp-evm.dts57 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
58 brightness-levels = <0 51 53 56 62 75 101 152 255>;
68 pinctrl-0 = <&matrix_keypad_default>;
80 linux,keymap = <0x00000201 /* P1 */
81 0x00010202 /* P2 */
82 0x01000067 /* UP */
83 0x0101006a /* RIGHT */
84 0x02000069 /* LEFT */
85 0x0201006c>; /* DOWN */
103 #clock-cells = <0>;
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/
H A Dcom.fuc32 ctx_object: .b32 0
35 ctx_dma_query: .b32 0
36 ctx_dma_src: .b32 0
37 ctx_dma_dst: .b32 0
40 ctx_query_address_high: .b32 0
41 ctx_query_address_low: .b32 0
42 ctx_query_counter: .b32 0
43 ctx_src_address_high: .b32 0
44 ctx_src_address_low: .b32 0
45 ctx_src_pitch: .b32 0
[all …]
/linux/drivers/usb/serial/
H A Dipw.c53 #define USB_IPW_MAGIC 0x6d02 /* magic number for ipw struct */
57 #define EVENT_BUFFER_SIZE 0xFF
58 #define CHAR2INT16(c1, c0) (((u32)((c1) & 0xff) << 8) + (u32)((c0) & 0xff))
61 #define IPW_VID 0x0bc3
62 #define IPW_PID 0x0001
69 ipw_sio_b256000 = 0x000e,
70 ipw_sio_b128000 = 0x001d,
71 ipw_sio_b115200 = 0x0020,
72 ipw_sio_b57600 = 0x0040,
73 ipw_sio_b56000 = 0x0042,
[all …]

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