Lines Matching +full:0 +full:x810
29 * store at 0 and some ESBs support doing a trigger via a
32 #define XIVE_ESB_STORE_EOI 0x400 /* Store */
33 #define XIVE_ESB_LOAD_EOI 0x000 /* Load */
34 #define XIVE_ESB_GET 0x800 /* Load */
35 #define XIVE_ESB_SET_PQ_00 0xc00 /* Load */
36 #define XIVE_ESB_SET_PQ_01 0xd00 /* Load */
37 #define XIVE_ESB_SET_PQ_10 0xe00 /* Load */
38 #define XIVE_ESB_SET_PQ_11 0xf00 /* Load */
46 #define XIVE_ESB_LD_ST_MO 0x40 /* Load-after-store ordering */
48 #define XIVE_ESB_VAL_P 0x2
49 #define XIVE_ESB_VAL_Q 0x1
50 #define XIVE_ESB_INVALID 0xFF
57 #define TM_QW0_USER 0x000 /* All rings */
58 #define TM_QW1_OS 0x010 /* Ring 0..2 */
59 #define TM_QW2_HV_POOL 0x020 /* Ring 0..1 */
60 #define TM_QW3_HV_PHYS 0x030 /* Ring 0..1 */
63 #define TM_NSR 0x0 /* + + - + */
64 #define TM_CPPR 0x1 /* - + - + */
65 #define TM_IPB 0x2 /* - + + + */
66 #define TM_LSMFB 0x3 /* - + + + */
67 #define TM_ACK_CNT 0x4 /* - + - - */
68 #define TM_INC 0x5 /* - + - + */
69 #define TM_AGE 0x6 /* - + - + */
70 #define TM_PIPR 0x7 /* - + - + */
72 #define TM_WORD0 0x0
73 #define TM_WORD1 0x4
79 #define TM_WORD2 0x8
80 #define TM_QW0W2_VU PPC_BIT32(0)
82 #define TM_QW1W2_VO PPC_BIT32(0)
85 #define TM_QW2W2_VP PPC_BIT32(0)
88 #define TM_QW3W2_VT PPC_BIT32(0)
102 * - Byte load from QW3[TM_WORD2] - Read VT||00000||LP||LE on thrd 0
109 #define TM_SPC_ACK_EBB 0x800 /* Load8 ack EBB to reg*/
110 #define TM_SPC_ACK_OS_REG 0x810 /* Load16 ack OS irq to reg */
111 #define TM_SPC_PUSH_USR_CTX 0x808 /* Store32 Push/Validate user context */
112 #define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user context */
113 #define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */
114 #define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS context to reg */
115 #define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool context to reg*/
116 #define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */
117 #define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd line */
118 #define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */
119 #define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even line */
120 #define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line */
124 #define TM_QW0_NSR_EB PPC_BIT8(0)
125 #define TM_QW1_NSR_EO PPC_BIT8(0)
126 #define TM_QW3_NSR_HE PPC_BITMASK8(0,1)
127 #define TM_QW3_NSR_HE_NONE 0