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/freebsd/sys/contrib/device-tree/Bindings/firmware/
H A Dnxp,imx95-scmi.yaml20 const: 0x81
28 const: 0x84
36 enum: [0, 1, 2, 3, 4, 5, 6, 7, 0x8000, 0x8001, 0x8002, 0x8003,
37 0x8004, 0x8005, 0x8006, 0x8007]
/freebsd/sys/contrib/dev/athk/
H A Dreg.h20 #define AR_MIBC 0x0040
21 #define AR_MIBC_COW 0x00000001
22 #define AR_MIBC_FMC 0x00000002
23 #define AR_MIBC_CMC 0x00000004
24 #define AR_MIBC_MCS 0x00000008
26 #define AR_STA_ID0 0x8000
27 #define AR_STA_ID1 0x8004
28 #define AR_STA_ID1_SADH_MASK 0x0000ffff
34 #define AR_BSSMSKL 0x80e0
35 #define AR_BSSMSKU 0x80e4
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/
H A DMinidumpConstants.def3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
39 HANDLE_MDMP_STREAM_TYPE(0x0003, ThreadList)
40 HANDLE_MDMP_STREAM_TYPE(0x0004, ModuleList)
41 HANDLE_MDMP_STREAM_TYPE(0x0005, MemoryList)
42 HANDLE_MDMP_STREAM_TYPE(0x0006, Exception)
43 HANDLE_MDMP_STREAM_TYPE(0x0007, SystemInfo)
44 HANDLE_MDMP_STREAM_TYPE(0x0008, ThreadExList)
45 HANDLE_MDMP_STREAM_TYPE(0x0009, Memory64List)
46 HANDLE_MDMP_STREAM_TYPE(0x000a, CommentA)
47 HANDLE_MDMP_STREAM_TYPE(0x000b, CommentW)
[all …]
H A DDwarf.def3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
38 #define DW_KIND_NONE 0
149 HANDLE_DW_TAG(0x0000, null, 2, DWARF, DW_KIND_NONE)
150 HANDLE_DW_TAG(0x0001, array_type, 2, DWARF, DW_KIND_TYPE)
151 HANDLE_DW_TAG(0x0002, class_type, 2, DWARF, DW_KIND_TYPE)
152 HANDLE_DW_TAG(0x0003, entry_point, 2, DWARF, DW_KIND_NONE)
153 HANDLE_DW_TAG(0x0004, enumeration_type, 2, DWARF, DW_KIND_TYPE)
154 HANDLE_DW_TAG(0x0005, formal_parameter, 2, DWARF, DW_KIND_NONE)
155 HANDLE_DW_TAG(0x0008, imported_declaration, 2, DWARF, DW_KIND_NONE)
156 HANDLE_DW_TAG(0x000a, label, 2, DWARF, DW_KIND_NONE)
[all …]
/freebsd/contrib/file/magic/Magdir/
H A Dmsx11 0 string/b MGS MSX Gigamix MGSDRV3 music file,
12 >6 ubeshort 0x0D0A
16 >>8 string >\0 \b, title: %s
19 >6 uleshort 0x80
20 >>0x2E uleshort 0
21 >>>0x30 string >\0 \b, title: %s
24 0 string/b KSCC KSS music file v1.03
25 >0xE byte 0
26 >>0xF byte&0x02 0 \b, soundchips: AY-3-8910, SCC(+)
27 >>0xF byte&0x02 2 \b, soundchip(s): SN76489
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/DebugInfo/CodeView/
H A DCodeViewTypes.def3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
38 TYPE_RECORD(LF_POINTER, 0x1002, Pointer)
39 TYPE_RECORD(LF_MODIFIER, 0x1001, Modifier)
40 TYPE_RECORD(LF_PROCEDURE, 0x1008, Procedure)
41 TYPE_RECORD(LF_MFUNCTION, 0x1009, MemberFunction)
42 TYPE_RECORD(LF_LABEL, 0x000e, Label)
43 TYPE_RECORD(LF_ARGLIST, 0x1201, ArgList)
45 TYPE_RECORD(LF_FIELDLIST, 0x1203, FieldList)
47 TYPE_RECORD(LF_ARRAY, 0x1503, Array)
48 TYPE_RECORD(LF_CLASS, 0x1504, Class)
[all …]
/freebsd/sys/dev/cxgb/common/
H A Dcxgb_mv88e1xxx.c35 #define MV_INTR_JABBER 0x0001
36 #define MV_INTR_POLARITY_CHNG 0x0002
37 #define MV_INTR_ENG_DETECT_CHNG 0x0010
38 #define MV_INTR_DOWNSHIFT 0x0020
39 #define MV_INTR_MDI_XOVER_CHNG 0x0040
40 #define MV_INTR_FIFO_OVER_UNDER 0x0080
41 #define MV_INTR_FALSE_CARRIER 0x0100
42 #define MV_INTR_SYMBOL_ERROR 0x0200
43 #define MV_INTR_LINK_CHNG 0x0400
44 #define MV_INTR_AUTONEG_DONE 0x0800
[all …]
/freebsd/sys/dev/pms/RefTisa/sallsdk/spc/
H A Dsahwreg.h34 /* Message Unit Registers - BAR0(0x10), BAR0(win) */
38 #define MSGU_IBDB_SET 0x20
39 #define MSGU_HOST_INT_STATUS 0x30
40 #define MSGU_HOST_INT_MASK 0x34
41 #define MSGU_IOPIB_INT_STATUS 0x40
42 #define MSGU_IOPIB_INT_MASK 0x44
43 #define MSGU_IBDB_CLEAR 0x70
44 #define MSGU_MSGU_CONTROL 0x74
45 #define MSGU_ODR 0x9C
46 #define MSGU_ODCR 0xA0
[all …]
/freebsd/sys/netinet/
H A Dsctp_header.h128 struct sctp_paramhdr ph; /* type = 0x8008 len = x */
461 #define SCTP_STREAM_RESET_RESULT_NOTHING_TO_DO 0x00000000 /* XXX: unused */
462 #define SCTP_STREAM_RESET_RESULT_PERFORMED 0x00000001
463 #define SCTP_STREAM_RESET_RESULT_DENIED 0x00000002
464 #define SCTP_STREAM_RESET_RESULT_ERR__WRONG_SSN 0x00000003 /* XXX: unused */
465 #define SCTP_STREAM_RESET_RESULT_ERR_IN_PROGRESS 0x00000004
466 #define SCTP_STREAM_RESET_RESULT_ERR_BAD_SEQNO 0x00000005
467 #define SCTP_STREAM_RESET_RESULT_IN_PROGRESS 0x00000006 /* XXX: unused */
499 struct sctp_paramhdr ph; /* type = 0x8002 */
504 struct sctp_paramhdr ph; /* type = 0x8003 */
[all …]
H A Dsctp_constants.h68 #define SCTP_MAX_CHUNK_LENGTH 0xffff
70 #define SCTP_MAX_CAUSE_LENGTH 0xffff
87 #define SCTP_KTHREAD_PAGES 0
235 #define SCTP_LOG_EVENT_UNKNOWN 0
265 /* default MULTIPLE_ASCONF mode enable(1)/disable(0) value (sysctl) */
266 #define SCTP_DEFAULT_MULTIPLE_ASCONFS 0
303 #define PROTO_SIGNATURE_A 0x30000000
304 #define SCTP_VERSION_NUMBER 0x3
306 #define MAX_TSN 0xffffffff
328 /* default max I can burst out after a fast retransmit, 0 disables it */
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsBranchExpansion.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
48 /// 0x8004 bnec a1,v0,<P+0x18>
49 /// 0x8008 beqc a1,a2,<P+0x54>
54 /// Here, if the instruction at 0x8004 is executed, the processor will raise an
55 /// exception as there is a control transfer instruction at 0x8008.
128 uint64_t Size = 0;
131 uint64_t Offset = 0;
183 char MipsBranchExpansion::ID = 0;
231 for (unsigned I = 0, E = Br.getDesc().getNumOperands(); I < E; ++I) { in getTargetMBB()
298 for (unsigned I = 0, E = MBBInfos.size(); I < E; ++I) { in initMBBInfo()
[all …]
/freebsd/sys/dev/bxe/
H A D57711_int_offsets.h31 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_SIZE
32 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_DATA_SIZE
33 { 0x28, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_SIZE
34 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_DATA_SIZE
35 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_DYNAMIC_HC_CONFIG_SIZE
36 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_MSG_SIZE
37 { 0x8, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_INDEX_SIZE
38 { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_INVALID_ASSERT_OPCODE
39 { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_RAM1_TEST_EVENT_ID
40 …{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_EVEN…
[all …]
H A D57712_int_offsets.h31 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_SIZE
32 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_DATA_SIZE
33 { 0x28, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_SIZE
34 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_DATA_SIZE
35 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_DYNAMIC_HC_CONFIG_SIZE
36 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_MSG_SIZE
37 { 0x8, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_INDEX_SIZE
38 { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_INVALID_ASSERT_OPCODE
39 { 0x3d, 0x0, 0x0, 0x0, 0x0}, // COMMON_RAM1_TEST_EVENT_ID
40 …{ 0x3c, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_EVEN…
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5210/
H A Dar5210reg.h28 #define PCI_VENDOR_ATHEROS 0x168c
30 #define PCI_PRODUCT_ATHEROS_AR5210 0x0007
31 #define PCI_PRODUCT_ATHEROS_AR5210_OLD 0x0004
34 #define AR_TXDP0 0x0000 /* TX queue pointer 0 register */
35 #define AR_TXDP1 0x0004 /* TX queue pointer 1 register */
36 #define AR_CR 0x0008 /* Command register */
37 #define AR_RXDP 0x000c /* RX queue descriptor ptr register */
38 #define AR_CFG 0x0014 /* Configuration and status register */
39 #define AR_ISR 0x001c /* Interrupt status register */
40 #define AR_IMR 0x0020 /* Interrupt mask register */
[all …]
/freebsd/sys/contrib/dev/athk/ath10k/
H A Dcoredump.c18 {0x800, 0x810},
19 {0x820, 0x82C},
20 {0x830, 0x8F4},
21 {0x90C, 0x91C},
22 {0xA14, 0xA18},
23 {0xA84, 0xA94},
24 {0xAA8, 0xAD4},
25 {0xADC, 0xB40},
26 {0x1000, 0x10A4},
27 {0x10BC, 0x111C},
[all …]
/freebsd/sys/arm64/iommu/
H A Dsmmureg.h36 #define SMMU_IDR0 0x000
38 #define IDR0_ST_LVL_M (0x3 << IDR0_ST_LVL_S)
39 #define IDR0_ST_LVL_LINEAR (0x0 << IDR0_ST_LVL_S) /* Linear Stream table*/
40 #define IDR0_ST_LVL_2 (0x1 << IDR0_ST_LVL_S) /* 2-level Stream Table*/
43 #define IDR0_STALL_MODEL_M (0x3 << IDR0_STALL_MODEL_S)
44 #define IDR0_STALL_MODEL_STALL (0x0 << IDR0_STALL_MODEL_S) /* Stall and Term*/
45 #define IDR0_STALL_MODEL_FORCE (0x2 << IDR0_STALL_MODEL_S) /* Stall is forced*/
47 #define IDR0_TTENDIAN_M (0x3 << IDR0_TTENDIAN_S)
48 #define IDR0_TTENDIAN_MIXED (0x0 << IDR0_TTENDIAN_S)
49 #define IDR0_TTENDIAN_LITTLE (0x2 << IDR0_TTENDIAN_S)
[all …]
/freebsd/sys/dev/qcom_gcc/
H A Dqcom_gcc_ipq4018_clock.c71 .clkdef.parent_cnt = 0, \
82 .clkdef.parent_cnt = 0, \
207 F_FEPLL(GCC_FEPLL_VCO, "gcc_fepll_vco", "xo", 0x2f020, 16, 8, 24, 5),
208 F_FEPLL(GCC_APSS_DDRPLL_VCO, "gcc_apps_ddrpll_vco", "xo", 0x2e020,
219 { 384000000, "gcc_apps_ddrpll_vco", 0xd, 0, 0 },
220 { 413000000, "gcc_apps_ddrpll_vco", 0xc, 0, 0 },
221 { 448000000, "gcc_apps_ddrpll_vco", 0xb, 0, 0 },
222 { 488000000, "gcc_apps_ddrpll_vco", 0xa, 0, 0 },
223 { 512000000, "gcc_apps_ddrpll_vco", 0x9, 0, 0 },
224 { 537000000, "gcc_apps_ddrpll_vco", 0x8, 0, 0 },
[all …]
/freebsd/sys/net/
H A Dethernet.h37 ((hasfcs) ? ETHER_CRC_LEN : 0) + \
38 (((etype) == ETHERTYPE_VLAN) ? ETHER_VLAN_ENCAP_LEN : 0))
48 #define ETHER_CRC_POLY_LE 0xedb88320
49 #define ETHER_CRC_POLY_BE 0x04c11db6
77 #define ETHER_IS_MULTICAST(addr) (*(addr) & 0x01) /* is address mcast/bcast? */
79 (((addr)[0] == 0x33) && ((addr)[1] == 0x33))
81 (((addr)[0] & (addr)[1] & (addr)[2] & \
82 (addr)[3] & (addr)[4] & (addr)[5]) == 0xff)
84 (((addr)[0] | (addr)[1] | (addr)[2] | \
85 (addr)[3] | (addr)[4] | (addr)[5]) == 0x00)
[all …]
/freebsd/sbin/nvmecontrol/modules/wdc/
H A Dwdc.c48 #define NONE 0xffffffffu
49 #define NONE64 0xffffffffffffffffull
51 #define OPT_END { NULL, 0, arg_none, NULL, NULL }
54 ….name = "wdc", .fn = wdc, .descr = "wdc vendor specific commands", .ctx_size = 0, .opts = NULL, .a…
67 .data_area = 0,
94 #define WDC_NVME_VID 0x1c58
95 #define WDC_NVME_VID_2 0x1b96
96 #define WDC_NVME_VID_3 0x15b7
98 #define WDC_NVME_TOC_SIZE 0x8
99 #define WDC_NVME_LOG_SIZE_HDR_LEN 0x8
[all …]
/freebsd/sys/dev/usb/
H A Dusbdevs50 * #define USB_VENDOR_VNDR 0x????
51 * #define USB_PRODUCT_VNDR_PRDCT 0x????
57 vendor UNKNOWN1 0x0053 Unknown vendor
58 vendor UNKNOWN2 0x0105 Unknown vendor
59 vendor EGALAX2 0x0123 eGalax, Inc.
60 vendor CHIPSBANK 0x0204 Chipsbank Microelectronics Co.
61 vendor HUMAX 0x02ad HUMAX
62 vendor QUAN 0x01e1 Quan
63 vendor LTS 0x0386 LTS
64 vendor BWCT 0x03da Bernd Walter Computer Technology
[all …]
/freebsd/sys/dev/isp/
H A Dispmbox.h41 #define MBOX_NO_OP 0x0000
42 #define MBOX_LOAD_RAM 0x0001
43 #define MBOX_EXEC_FIRMWARE 0x0002
44 #define MBOX_LOAD_FLASH_FIRMWARE 0x0003
45 #define MBOX_WRITE_RAM_WORD 0x0004
46 #define MBOX_READ_RAM_WORD 0x0005
47 #define MBOX_MAILBOX_REG_TEST 0x0006
48 #define MBOX_VERIFY_CHECKSUM 0x0007
49 #define MBOX_ABOUT_FIRMWARE 0x0008
50 #define MBOX_LOAD_RISC_RAM_2100 0x0009
[all …]
/freebsd/sys/powerpc/include/
H A Dspr.h35 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val))
38 __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \
48 mfmsr %0; \
49 insrdi %0,%5,1,0; \
50 mtmsrd %0; \
58 clrldi %0,%0,1; \
59 mtmsrd %0; \
66 mfmsr %0; \
[all...]
/freebsd/sys/dev/ath/ath_hal/ar5211/
H A Dar5211reg.h32 #define AR_CR 0x0008 /* control register */
33 #define AR_RXDP 0x000C /* receive queue descriptor pointer */
34 #define AR_CFG 0x0014 /* configuration and status register */
35 #define AR_IER 0x0024 /* Interrupt enable register */
36 #define AR_RTSD0 0x0028 /* RTS Duration Parameters 0 */
37 #define AR_RTSD1 0x002c /* RTS Duration Parameters 1 */
38 #define AR_TXCFG 0x0030 /* tx DMA size config register */
39 #define AR_RXCFG 0x0034 /* rx DMA size config register */
40 #define AR5211_JUMBO_LAST 0x0038 /* Jumbo descriptor last address */
41 #define AR_MIBC 0x0040 /* MIB control register */
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212reg.h27 #define AR_CR 0x0008 /* MAC control register */
28 #define AR_RXDP 0x000C /* MAC receive queue descriptor pointer */
29 #define AR_CFG 0x0014 /* MAC configuration and status register */
30 #define AR_IER 0x0024 /* MAC Interrupt enable register */
31 /* 0x28 is RTSD0 on the 5211 */
32 /* 0x2c is RTSD1 on the 5211 */
33 #define AR_TXCFG 0x0030 /* MAC tx DMA size config register */
34 #define AR_RXCFG 0x0034 /* MAC rx DMA size config register */
35 /* 0x38 is the jumbo descriptor address on the 5211 */
36 #define AR_MIBC 0x0040 /* MAC MIB control register */
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/westmereep-dp/
H A Dcache.json4 "Counter": "0,1",
5 "EventCode": "0x63",
8 "UMask": "0x2"
12 "Counter": "0,1",
13 "EventCode": "0x63",
16 "UMask": "0x1"
20 "Counter": "0,1",
21 "EventCode": "0x51",
24 "UMask": "0x4"
28 "Counter": "0,1",
[all …]

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