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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx51-digi-connectcore-som.dtsi15 reg = <0x90000000 0x08000000>;
21 pinctrl-0 = <&pinctrl_ecspi1>;
25 pmic: mc13892@0 {
27 pinctrl-0 = <&pinctrl_mc13892>;
31 reg = <0>;
130 pinctrl-0 = <&pinctrl_esdhc1>;
137 pinctrl-0 = <&pinctrl_esdhc2>;
150 pinctrl-0 = <&pinctrl_fec>;
158 pinctrl-0 = <&pinctrl_i2c2>;
167 pinctrl-0 = <&pinctrl_mma7455l>;
[all …]
H A Dimx53-mba53.dts20 pwms = <&pwm2 0 50000 0>;
21 brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
23 enable-gpios = <&gpio7 7 0>;
30 pinctrl-0 = <&pinctrl_disp1_1>;
44 gpio = <&gpio2 5 0>;
73 pinctrl-0 = <&pinctrl_lvds1_1>;
80 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
81 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
82 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
83 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
[all …]
H A Dimx53-tqma53.dtsi15 reg = <0x70000000 0x40000000>; /* Up to 1GiB */
29 pinctrl-0 = <&pinctrl_esdhc2>,
39 pinctrl-0 = <&pinctrl_uart3>;
45 pinctrl-0 = <&pinctrl_ecspi1>;
53 pinctrl-0 = <&pinctrl_esdhc3>;
62 pinctrl-0 = <&pinctrl_hog>;
66 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */
67 MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 /* LCD_BLT_EN */
68 MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 /* LCD_RESET */
69 MX53_PAD_PATA_DATA5__GPIO2_5 0x80000000 /* LCD_POWER */
[all …]
H A Dimx25-pdk.dts16 reg = <0x80000000 0x4000000>;
19 reg_fec_3v3: regulator-0 {
24 gpio = <&gpio2 3 0>;
47 gpio = <&gpio4 6 0>;
67 fsl,pcr = <0xfa208b80>;
88 pinctrl-0 = <&pinctrl_audmux>;
94 pinctrl-0 = <&pinctrl_can1>;
101 pinctrl-0 = <&pinctrl_esdhc1>;
103 wp-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
110 pinctrl-0 = <&pinctrl_fec>;
[all …]
H A Dimx53-tx53.dtsi19 reg = <0x70000000 0>;
33 clock-frequency = <0>;
39 #clock-cells = <0>;
46 pinctrl-0 = <&pinctrl_gpio_key>;
59 pinctrl-0 = <&pinctrl_stk5led>;
88 pinctrl-0 = <&pinctrl_can_xcvr>;
98 pinctrl-0 = <&pinctrl_usbh1_vbus>;
109 pinctrl-0 = <&pinctrl_usbotg_vbus>;
131 pinctrl-0 = <&pinctrl_ssi1>;
137 pinctrl-0 = <&pinctrl_can1>;
[all …]
H A Dimx25-eukrea-cpuimx25.dtsi14 reg = <0x80000000 0x4000000>; /* 64M */
21 pinctrl-0 = <&pinctrl_fec>;
27 pinctrl-0 = <&pinctrl_i2c1>;
32 reg = <0x51>;
40 MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
41 MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0
42 MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
43 MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
44 MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
45 MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
[all …]
H A Dimx25-eukrea-mbimxsd25-baseboard.dts19 pinctrl-0 = <&pinctrl_gpiokeys>;
32 pinctrl-0 = <&pinctrl_gpioled>;
52 pinctrl-0 = <&pinctrl_audmux>;
58 pinctrl-0 = <&pinctrl_esdhc1>;
66 reg = <0x1a>;
74 MX25_PAD_KPP_COL3__AUD5_TXFS 0xe0
75 MX25_PAD_KPP_COL2__AUD5_TXC 0xe0
76 MX25_PAD_KPP_COL1__AUD5_RXD 0xe0
77 MX25_PAD_KPP_COL0__AUD5_TXD 0xe0
83 MX25_PAD_SD1_CMD__ESDHC1_CMD 0x400000c0
[all …]
H A Dimx53-tx53-x13x.dts22 pwms = <&pwm2 0 500000 0>;
25 0 1 2 3 4 5 6 7 8 9
42 pwms = <&pwm1 0 500000 0>;
45 0 1 2 3 4 5 6 7 8 9
83 pinctrl-0 = <&pinctrl_i2c3>;
91 reg = <0x0a>;
92 #sound-dai-cells = <0>;
102 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
103 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
104 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
[all …]
H A Dimx25-karo-tx25.dts17 reg_fec_phy: regulator-0 {
22 gpio = <&gpio4 9 0>;
28 reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
35 MX25_PAD_UART1_TXD__UART1_TXD 0x00000020
36 MX25_PAD_UART1_RXD__UART1_RXD 0x000000a0
37 MX25_PAD_UART1_CTS__UART1_CTS 0x00000060
38 MX25_PAD_UART1_RTS__UART1_RTS 0x000000e0
44 MX25_PAD_D11__GPIO_4_9 0x00000021 /* FEC PHY power on pin */
45 MX25_PAD_D13__GPIO_4_7 0x000000a1 /* FEC reset */
46 MX25_PAD_FEC_MDC__FEC_MDC 0x00000060
[all …]
/linux/sound/soc/amd/include/
H A Dacp_2_2_sh_mask.h27 #define ACP_DMA_CNTL_0__DMAChRst_MASK 0x1
28 #define ACP_DMA_CNTL_0__DMAChRst__SHIFT 0x0
29 #define ACP_DMA_CNTL_0__DMAChRun_MASK 0x2
30 #define ACP_DMA_CNTL_0__DMAChRun__SHIFT 0x1
31 #define ACP_DMA_CNTL_0__DMAChIOCEn_MASK 0x4
32 #define ACP_DMA_CNTL_0__DMAChIOCEn__SHIFT 0x2
33 #define ACP_DMA_CNTL_0__Circular_DMA_En_MASK 0x8
34 #define ACP_DMA_CNTL_0__Circular_DMA_En__SHIFT 0x3
35 #define ACP_DMA_CNTL_0__DMAChGracefulRstEn_MASK 0x10
36 #define ACP_DMA_CNTL_0__DMAChGracefulRstEn__SHIFT 0x4
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dsi_blit_shaders.h29 0xc0066900,
30 0x00000000,
31 0x00000060, /* DB_RENDER_CONTROL */
32 0x00000000, /* DB_COUNT_CONTROL */
33 0x00000000, /* DB_DEPTH_VIEW */
34 0x0000002a, /* DB_RENDER_OVERRIDE */
35 0x00000000, /* DB_RENDER_OVERRIDE2 */
36 0x00000000, /* DB_HTILE_DATA_BASE */
38 0xc0046900,
39 0x00000008,
[all …]
H A Dcik_blit_shaders.h32 0xc0066900,
33 0x00000000,
34 0x00000060, /* DB_RENDER_CONTROL */
35 0x00000000, /* DB_COUNT_CONTROL */
36 0x00000000, /* DB_DEPTH_VIEW */
37 0x0000002a, /* DB_RENDER_OVERRIDE */
38 0x00000000, /* DB_RENDER_OVERRIDE2 */
39 0x00000000, /* DB_HTILE_DATA_BASE */
41 0xc0046900,
42 0x00000008,
[all …]
H A Dcayman_blit_shaders.h40 0xc0066900,
41 0x00000000,
42 0x00000060, /* DB_RENDER_CONTROL */
43 0x00000000, /* DB_COUNT_CONTROL */
44 0x00000000, /* DB_DEPTH_VIEW */
45 0x0000002a, /* DB_RENDER_OVERRIDE */
46 0x00000000, /* DB_RENDER_OVERRIDE2 */
47 0x00000000, /* DB_HTILE_DATA_BASE */
49 0xc0026900,
50 0x0000000a,
[all …]
H A Devergreen_blit_shaders.h41 0xc0016900,
42 0x0000023b,
43 0x00000000, /* SQ_LDS_ALLOC_PS */
45 0xc0066900,
46 0x00000240,
47 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
48 0x00000000,
49 0x00000000,
50 0x00000000,
51 0x00000000,
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dpsp_v3_1.c52 #define smnMP1_FIRMWARE_FLAGS 0x3010028
61 int err = 0; in psp_v3_1_init_microcode()
75 return 0; in psp_v3_1_init_microcode()
81 uint32_t psp_gfxdrv_command_reg = 0; in psp_v3_1_bootloader_load_sysdrv()
88 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); in psp_v3_1_bootloader_load_sysdrv()
90 return 0; in psp_v3_1_bootloader_load_sysdrv()
93 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), in psp_v3_1_bootloader_load_sysdrv()
94 0x80000000, 0x80000000, 0); in psp_v3_1_bootloader_load_sysdrv()
102 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, in psp_v3_1_bootloader_load_sysdrv()
105 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, in psp_v3_1_bootloader_load_sysdrv()
[all …]
/linux/arch/mips/include/asm/mach-malta/
H A Dspaces.h17 * 0x00000000 - 0x0fffffff: 1st RAM region, 256MB
18 * 0x10000000 - 0x1bffffff: GIC and CPC Control Registers
19 * 0x1c000000 - 0x1fffffff: I/O And Flash
20 * 0x20000000 - 0x7fffffff: 2nd RAM region, 1.5GB
21 * 0x80000000 - 0xffffffff: Physical memory aliases to 0x0 (2GB)
23 * The kernel is still located in 0x80000000(kseg0). However,
24 * the physical mask has been shifted to 0x80000000 which exploits the alias
27 * words, the 0x80000000 virtual address maps to 0x80000000 physical address
28 * which in turn aliases to 0x0. We do this in order to be able to use a flat
29 * 2GB of memory (0x80000000 - 0xffffffff) so we can avoid the I/O hole in
[all …]
/linux/arch/powerpc/boot/dts/
H A Dicon.dts18 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
49 reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
[all …]
H A Dkatmai.dts22 dcr-parent = <&{/cpus/cpu@0}>;
33 #size-cells = <0>;
35 cpu@0 {
38 reg = <0x00000000>;
39 clock-frequency = <0>; /* Filled in by zImage */
40 timebase-frequency = <0>; /* Filled in by zImage */
53 reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
59 cell-index = <0>;
60 dcr-reg = <0x0c0 0x009>;
61 #address-cells = <0>;
[all …]
H A Dcurrituck.dts13 /memreserve/ 0x01f00000 0x00100000; // spin table
20 dcr-parent = <&{/cpus/cpu@0}>;
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
58 cpu-release-addr = <0x0 0x01f00000>;
64 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
70 dcr-reg = <0xffc00000 0x00040000>;
71 #address-cells = <0>;
72 #size-cells = <0>;
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fault/
H A Dgv100.c34 struct nvkm_fault_buffer *buffer = fault->buffer[0]; in gv100_fault_buffer_process()
45 const u32 instlo = nvkm_ro32(mem, base + 0x00); in gv100_fault_buffer_process()
46 const u32 insthi = nvkm_ro32(mem, base + 0x04); in gv100_fault_buffer_process()
47 const u32 addrlo = nvkm_ro32(mem, base + 0x08); in gv100_fault_buffer_process()
48 const u32 addrhi = nvkm_ro32(mem, base + 0x0c); in gv100_fault_buffer_process()
49 const u32 timelo = nvkm_ro32(mem, base + 0x10); in gv100_fault_buffer_process()
50 const u32 timehi = nvkm_ro32(mem, base + 0x14); in gv100_fault_buffer_process()
51 const u32 info0 = nvkm_ro32(mem, base + 0x18); in gv100_fault_buffer_process()
52 const u32 info1 = nvkm_ro32(mem, base + 0x1c); in gv100_fault_buffer_process()
56 get = 0; in gv100_fault_buffer_process()
[all …]
/linux/include/linux/
H A Dfsl_ifc.h26 #define FSL_IFC_VERSION_MASK 0x0F0F0000
27 #define FSL_IFC_VERSION_1_0_0 0x01000000
28 #define FSL_IFC_VERSION_1_1_0 0x01010000
29 #define FSL_IFC_VERSION_2_0_0 0x02000000
37 #define CSPR_BA 0xFFFF0000
39 #define CSPR_PORT_SIZE 0x00000180
42 #define CSPR_PORT_SIZE_8 0x00000080
44 #define CSPR_PORT_SIZE_16 0x00000100
46 #define CSPR_PORT_SIZE_32 0x00000180
48 #define CSPR_WP 0x00000040
[all …]
/linux/arch/x86/pci/
H A Dearly.c14 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in read_pci_config()
15 v = inl(0xcfc); in read_pci_config()
22 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in read_pci_config_byte()
23 v = inb(0xcfc + (offset&3)); in read_pci_config_byte()
30 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in read_pci_config_16()
31 v = inw(0xcfc + (offset&2)); in read_pci_config_16()
38 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in write_pci_config()
39 outl(val, 0xcfc); in write_pci_config()
44 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in write_pci_config_byte()
45 outb(val, 0xcfc + (offset&3)); in write_pci_config_byte()
[all …]
/linux/arch/powerpc/platforms/embedded6xx/
H A Dmpc10x.h24 * Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff
25 * Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff
26 * PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000
29 * Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff
30 * Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff
31 * PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000
40 #define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA)
41 #define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA)
42 #define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA)
49 #define MPC10X_MAPA_CNFG_ADDR 0x80000cf8
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt8135-apmixedsys.c38 PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000000, 0, 21, 0x204, 24, 0x0, 0x204, 0),
39 PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000000, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0),
40 …PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000000, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x2…
41 …PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000000, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x23…
42 …PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000000, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, …
43 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000000, 0, 21, 0x278, 6, 0x0, 0x27c, 0),
44 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000000, 0, 31, 0x294, 6, 0x0, 0x298, 0),
45 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
46 PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000000, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0),
47 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x308, 0),
[all …]
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_edma0_core_masks.h24 #define DCORE0_EDMA0_CORE_CFG_0_EN_SHIFT 0
25 #define DCORE0_EDMA0_CORE_CFG_0_EN_MASK 0x1
28 #define DCORE0_EDMA0_CORE_CFG_1_HALT_SHIFT 0
29 #define DCORE0_EDMA0_CORE_CFG_1_HALT_MASK 0x1
31 #define DCORE0_EDMA0_CORE_CFG_1_FLUSH_MASK 0x2
34 #define DCORE0_EDMA0_CORE_PROT_VAL_SHIFT 0
35 #define DCORE0_EDMA0_CORE_PROT_VAL_MASK 0x1
37 #define DCORE0_EDMA0_CORE_PROT_ERR_VAL_MASK 0x2
40 #define DCORE0_EDMA0_CORE_CKG_HBW_RBUF_SHIFT 0
41 #define DCORE0_EDMA0_CORE_CKG_HBW_RBUF_MASK 0x1
[all …]

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