52 #define smnMP1_FIRMWARE_FLAGS 0x3010028
61 	int err = 0;  in psp_v3_1_init_microcode()
75 	return 0;  in psp_v3_1_init_microcode()
81 	uint32_t psp_gfxdrv_command_reg = 0;  in psp_v3_1_bootloader_load_sysdrv()
88 	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);  in psp_v3_1_bootloader_load_sysdrv()
90 		return 0;  in psp_v3_1_bootloader_load_sysdrv()
93 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),  in psp_v3_1_bootloader_load_sysdrv()
94 			   0x80000000, 0x80000000, 0);  in psp_v3_1_bootloader_load_sysdrv()
102 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,  in psp_v3_1_bootloader_load_sysdrv()
105 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,  in psp_v3_1_bootloader_load_sysdrv()
111 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),  in psp_v3_1_bootloader_load_sysdrv()
112 			   0x80000000, 0x80000000, 0);  in psp_v3_1_bootloader_load_sysdrv()
120 	unsigned int psp_gfxdrv_command_reg = 0;  in psp_v3_1_bootloader_load_sos()
127 	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);  in psp_v3_1_bootloader_load_sos()
129 		return 0;  in psp_v3_1_bootloader_load_sos()
132 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),  in psp_v3_1_bootloader_load_sos()
133 			   0x80000000, 0x80000000, 0);  in psp_v3_1_bootloader_load_sos()
141 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,  in psp_v3_1_bootloader_load_sos()
144 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,  in psp_v3_1_bootloader_load_sos()
149 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),  in psp_v3_1_bootloader_load_sos()
150 			   RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0,  in psp_v3_1_bootloader_load_sos()
161 	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);  in psp_v3_1_reroute_ih()
165 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);  in psp_v3_1_reroute_ih()
166 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);  in psp_v3_1_reroute_ih()
167 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);  in psp_v3_1_reroute_ih()
170 	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),  in psp_v3_1_reroute_ih()
171 		     0x80000000, 0x8000FFFF, 0);  in psp_v3_1_reroute_ih()
174 	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);  in psp_v3_1_reroute_ih()
177 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);  in psp_v3_1_reroute_ih()
178 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);  in psp_v3_1_reroute_ih()
179 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);  in psp_v3_1_reroute_ih()
182 	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),  in psp_v3_1_reroute_ih()
183 		     0x80000000, 0x8000FFFF, 0);  in psp_v3_1_reroute_ih()
189 	int ret = 0;  in psp_v3_1_ring_create()
190 	unsigned int psp_ring_reg = 0;  in psp_v3_1_ring_create()
197 		ring->ring_wptr = 0;  in psp_v3_1_ring_create()
206 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);  in psp_v3_1_ring_create()
209 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);  in psp_v3_1_ring_create()
214 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg);  in psp_v3_1_ring_create()
221 			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),  in psp_v3_1_ring_create()
222 			0x80000000, 0x8000FFFF, 0);  in psp_v3_1_ring_create()
227 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);  in psp_v3_1_ring_create()
230 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);  in psp_v3_1_ring_create()
233 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);  in psp_v3_1_ring_create()
237 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);  in psp_v3_1_ring_create()
244 			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),  in psp_v3_1_ring_create()
245 			0x80000000, 0x8000FFFF, 0);  in psp_v3_1_ring_create()
253 	int ret = 0;  in psp_v3_1_ring_stop()
258 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,  in psp_v3_1_ring_stop()
261 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,  in psp_v3_1_ring_stop()
270 			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),  in psp_v3_1_ring_stop()
271 			0x80000000, 0x80000000, 0);  in psp_v3_1_ring_stop()
274 			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),  in psp_v3_1_ring_stop()
275 			0x80000000, 0x80000000, 0);  in psp_v3_1_ring_stop()
283 	int ret = 0;  in psp_v3_1_ring_destroy()
303 	reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000);  in psp_v3_1_smu_reload_quirk()
313 	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);  in psp_v3_1_mode1_reset()
315 	ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, 0);  in psp_v3_1_mode1_reset()
327 	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);  in psp_v3_1_mode1_reset()
329 	ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, 0);  in psp_v3_1_mode1_reset()
338 	return 0;  in psp_v3_1_mode1_reset()
349 		data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);  in psp_v3_1_ring_get_wptr()
358 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);  in psp_v3_1_ring_set_wptr()
360 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,  in psp_v3_1_ring_set_wptr()
364 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);  in psp_v3_1_ring_set_wptr()