Home
last modified time | relevance | path

Searched +full:0 +full:x7c000000 (Results 1 – 25 of 32) sorted by relevance

12

/linux/arch/powerpc/platforms/embedded6xx/
H A Dholly.c43 #define HOLLY_PCI_CFG_PHYS 0x7c000000
48 if (bus == 0 && PCI_SLOT(devfn) == 0) in holly_exclude_device()
64 lut_addr = 0x900; in holly_remap_bridge()
65 for (i = 0; i < 31; i++) { in holly_remap_bridge()
66 tsi108_write_reg(TSI108_PB_OFFSET + lut_addr, 0x00000201); in holly_remap_bridge()
68 tsi108_write_reg(TSI108_PB_OFFSET + lut_addr, 0x0); in holly_remap_bridge()
73 tsi108_write_reg(TSI108_PB_OFFSET + lut_addr, 0x00000241); in holly_remap_bridge()
75 tsi108_write_reg(TSI108_PB_OFFSET + lut_addr, 0x0); in holly_remap_bridge()
78 tsi108_write_reg(TSI108_PCI_PFAB_IO_UPPER, 0x0); in holly_remap_bridge()
79 tsi108_write_reg(TSI108_PCI_PFAB_IO, 0x1); in holly_remap_bridge()
[all …]
/linux/arch/microblaze/include/asm/
H A Dpvr.h13 #define PVR_MSR_BIT 0x400
22 #define PVR0_PVR_FULL_MASK 0x80000000
23 #define PVR0_USE_BARREL_MASK 0x40000000
24 #define PVR0_USE_DIV_MASK 0x20000000
25 #define PVR0_USE_HW_MUL_MASK 0x10000000
26 #define PVR0_USE_FPU_MASK 0x08000000
27 #define PVR0_USE_EXC_MASK 0x04000000
28 #define PVR0_USE_ICACHE_MASK 0x02000000
29 #define PVR0_USE_DCACHE_MASK 0x01000000
30 #define PVR0_USE_MMU 0x00800000
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7925/
H A Dregs.h9 #define MT_MDP_BASE 0x820cc800
12 #define MT_MDP_DCR0 MT_MDP(0x000)
16 #define MT_MDP_DCR1 MT_MDP(0x004)
19 #define MT_MDP_BNRCFR0(_band) MT_MDP(0x090 + ((_band) << 8))
24 #define MT_MDP_BNRCFR1(_band) MT_MDP(0x094 + ((_band) << 8))
28 #define MT_MDP_TO_HIF 0
31 #define MT_WFDMA0_HOST_INT_ENA MT_WFDMA0(0x204)
32 #define MT_WFDMA0_HOST_INT_DIS MT_WFDMA0(0x22c)
65 #define MT_RX_DATA_RING_BASE MT_WFDMA0(0x500)
67 #define MT_INFRA_CFG_BASE 0xd1000
[all …]
/linux/arch/arm/mach-footbridge/include/mach/
H A Dhardware.h13 * 0xff800000 0x40000000 1MB X-Bus
14 * 0xff000000 0x7c000000 1MB PCI I/O space
15 * 0xfe000000 0x42000000 1MB CSR
16 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
17 * 0xfc000000 0x79000000 1MB PCI IACK/special space
18 * 0xfb000000 0x7a000000 16MB PCI Config type 1
19 * 0xfa000000 0x7b000000 16MB PCI Config type 0
20 * 0xf9000000 0x50000000 1MB Cache flush
21 * 0xf0000000 0x80000000 16MB ISA memory
24 #define XBUS_SIZE 0x00100000
[all …]
/linux/arch/arm/mach-s3c/
H A Dmap-s3c64xx.h22 #define S3C64XX_PA_XM0CSN0 (0x10000000)
23 #define S3C64XX_PA_XM0CSN1 (0x18000000)
24 #define S3C64XX_PA_XM0CSN2 (0x20000000)
25 #define S3C64XX_PA_XM0CSN3 (0x28000000)
26 #define S3C64XX_PA_XM0CSN4 (0x30000000)
27 #define S3C64XX_PA_XM0CSN5 (0x38000000)
30 #define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000))
31 #define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0)
35 #define S3C_PA_UART (0x7F005000)
36 #define S3C_PA_UART0 (S3C_PA_UART + 0x00)
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie-x1e80100.yaml94 reg = <0 0x01c08000 0 0x3000>,
95 <0 0x7c000000 0 0xf1d>,
96 <0 0x7c000f40 0 0xa8>,
97 <0 0x7c001000 0 0x1000>,
98 <0 0x7c100000 0 0x100000>,
99 <0 0x01c0b000 0 0x1000>;
101 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
102 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
104 bus-range = <0x00 0xff>;
106 linux,pci-domain = <0>;
[all …]
/linux/arch/sh/include/asm/
H A Dprocessor_32.h19 #define CCN_PVR 0xff000030
20 #define CCN_CVR 0xff000040
21 #define CCN_PRR 0xff000044
26 * Since SH7709 and SH7750 have "area 7", we can't use 0x7c000000--0x7fffffff
28 #define TASK_SIZE 0x7c000000UL
48 #define SR_DSP 0x00001000
49 #define SR_IMASK 0x000000f0
50 #define SR_FD 0x00008000
51 #define SR_MD 0x40000000
53 #define SR_USER_MASK 0x00000303 // M, Q, S, T bits
[all …]
/linux/arch/arm/include/asm/hardware/
H A Ddec21285.h9 #define DC21285_PCI_IACK 0x79000000
10 #define DC21285_ARMCSR_BASE 0x42000000
11 #define DC21285_PCI_TYPE_0_CONFIG 0x7b000000
12 #define DC21285_PCI_TYPE_1_CONFIG 0x7a000000
13 #define DC21285_OUTBOUND_WRITE_FLUSH 0x78000000
14 #define DC21285_FLASH 0x41000000
15 #define DC21285_PCI_IO 0x7c000000
16 #define DC21285_PCI_MEM 0x80000000
26 * The footbridge is programmed to expose the system RAM at 0xe0000000.
27 * The requirement is that the RAM isn't placed at bus address 0, which
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_0_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_8_2_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_8_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7921/
H A Dpci.c17 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961),
19 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922),
21 { PCI_DEVICE(PCI_VENDOR_ID_ITTIM, 0x7922),
23 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608),
25 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616),
27 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7920),
70 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ in __mt7921_reg_addr()
71 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ in __mt7921_reg_addr()
72 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ in __mt7921_reg_addr()
73 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ in __mt7921_reg_addr()
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2711.dtsi21 #clock-cells = <0>;
28 #clock-cells = <0>;
41 ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
42 <0x7c000000 0x0 0xfc000000 0x02000000>,
43 <0x40000000 0x0 0xff800000 0x00800000>;
45 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;
53 reg = <0x40000000 0x100>;
60 reg = <0x40041000 0x1000>,
61 <0x40042000 0x2000>,
62 <0x40044000 0x2000>,
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Dfvp-base-revc.dts15 /memreserve/ 0x80000000 0x00010000;
45 #size-cells = <0>;
50 CPU_SLEEP_0: cpu-sleep-0 {
53 arm,psci-suspend-param = <0x0010000>;
60 CLUSTER_SLEEP_0: cluster-sleep-0 {
63 arm,psci-suspend-param = <0x1010000>;
71 cpu0: cpu@0 {
74 reg = <0x0 0x000>;
76 i-cache-size = <0x8000>;
79 d-cache-size = <0x8000>;
[all …]
/linux/arch/arm/kernel/
H A Dhead.S30 * the least significant 16 bits to be 0x8000, but we could probably
31 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
34 #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
35 #error KERNEL_RAM_VADDR must start at 0xXXXX8000
40 #define PG_DIR_SIZE 0x5000
43 #define PG_DIR_SIZE 0x4000
60 .long 0
61 .long 0
63 .long 0
64 .long 0
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dregs.h37 #define MT_HW_REV MT_HW_INFO(0x000)
38 #define MT_HW_CHIPID MT_HW_INFO(0x008)
39 #define MT_TOP_STRAP_STA MT_HW_INFO(0x010)
42 #define MT_TOP_OFF_RSV 0x1128
45 #define MT_TOP_MISC2 ((dev)->reg_map[MT_TOP_CFG_BASE] + 0x134)
46 #define MT_TOP_MISC2_FW_STATE GENMASK(2, 0)
51 #define MT_MCU_BASE 0x2000
54 #define MT_MCU_PCIE_REMAP_1 MT_MCU(0x500)
55 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
57 #define MT_PCIE_REMAP_BASE_1 0x40000
[all …]
/linux/arch/powerpc/include/asm/
H A Dppc-opcode.h13 #define __REG_R0 0
46 #define __REGA0_0 0
80 #define _R0 0
113 #define IMM_L(i) ((uintptr_t)(i) & 0xffff)
114 #define IMM_DS(i) ((uintptr_t)(i) & 0xfffc)
115 #define IMM_DQ(i) ((uintptr_t)(i) & 0xfff0)
116 #define IMM_D0(i) (((uintptr_t)(i) >> 16) & 0x3ffff)
122 * top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000).
128 (((uintptr_t)(i) & 0x8000) >> 15))
133 #define IMM_H18(i) (((uintptr_t)(i)>>16) & 0x3ffff)
[all …]
H A Dcpm2.h20 #define CPM_CR_RST ((uint)0x80000000)
21 #define CPM_CR_PAGE ((uint)0x7c000000)
22 #define CPM_CR_SBLOCK ((uint)0x03e00000)
23 #define CPM_CR_FLG ((uint)0x00010000)
24 #define CPM_CR_MCN ((uint)0x00003fc0)
25 #define CPM_CR_OPCODE ((uint)0x0000000f)
29 #define CPM_CR_SCC1_SBLOCK (0x04)
30 #define CPM_CR_SCC2_SBLOCK (0x05)
31 #define CPM_CR_SCC3_SBLOCK (0x06)
32 #define CPM_CR_SCC4_SBLOCK (0x07)
[all …]
/linux/drivers/media/platform/nxp/
H A Dimx-pxp.h13 #define HW_PXP_CTRL (0x00000000)
14 #define HW_PXP_CTRL_SET (0x00000004)
15 #define HW_PXP_CTRL_CLR (0x00000008)
16 #define HW_PXP_CTRL_TOG (0x0000000c)
18 #define BM_PXP_CTRL_SFTRST 0x80000000
21 #define BM_PXP_CTRL_CLKGATE 0x40000000
24 #define BM_PXP_CTRL_RSVD4 0x20000000
27 #define BM_PXP_CTRL_EN_REPEAT 0x10000000
30 #define BM_PXP_CTRL_ENABLE_ROTATE1 0x08000000
33 #define BM_PXP_CTRL_ENABLE_ROTATE0 0x04000000
[all …]
/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-reg.h107 #define CLEAR_FLAG_SFT 0
108 #define CLEAR_FLAG_MASK_SFT BIT(0)
153 #define AUDIO_AFE_ON_SFT 0
154 #define AUDIO_AFE_ON_MASK_SFT BIT(0)
157 #define AFE_ON_RETM_SFT 0
158 #define AFE_ON_RETM_MASK_SFT BIT(0)
187 #define I2S_EN_SFT 0
188 #define I2S_EN_MASK_SFT BIT(0)
209 #define I2S2_EN_SFT 0
210 #define I2S2_EN_MASK_SFT BIT(0)
[all …]
/linux/arch/mips/kernel/
H A Dtraps.c187 i = 0; in show_stacktrace()
189 if (i && ((i % (64 / field)) == 0)) { in show_stacktrace()
203 pr_cont(" %0*lx", field, stackdata); in show_stacktrace()
217 regs.regs[31] = 0; in show_stack()
218 regs.cp0_epc = 0; in show_stack()
222 regs.regs[31] = 0; in show_stack()
277 for (i = 0; i < 32; ) { in __show_regs()
278 if ((i % 4) == 0) in __show_regs()
280 if (i == 0) in __show_regs()
281 pr_cont(" %0*lx", field, 0UL); in __show_regs()
[all …]
/linux/drivers/net/ethernet/sun/
H A Dniu.h10 #define PIO 0x000000UL
11 #define FZC_PIO 0x080000UL
12 #define FZC_MAC 0x180000UL
13 #define FZC_IPP 0x280000UL
14 #define FFLP 0x300000UL
15 #define FZC_FFLP 0x380000UL
16 #define PIO_VADDR 0x400000UL
17 #define ZCP 0x500000UL
18 #define FZC_ZCP 0x580000UL
19 #define DMC 0x600000UL
[all …]
/linux/drivers/net/ethernet/toshiba/
H A Dtc35815.c54 TC35815CF = 0,
72 {0,}
86 __u32 DMA_Ctl; /* 0x00 */
94 __u32 FDA_Lim; /* 0x20 */
101 __u32 MAC_Ctl; /* 0x40 */
109 __u32 CAM_Adr; /* 0x60 */
123 #define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */
124 #define DMA_RxAlign_1 0x00400000
125 #define DMA_RxAlign_2 0x00800000
126 #define DMA_RxAlign_3 0x00c00000
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_enum.h28 NUMBER_UNORM = 0x0,
29 NUMBER_SNORM = 0x1,
30 NUMBER_USCALED = 0x2,
31 NUMBER_SSCALED = 0x3,
32 NUMBER_UINT = 0x4,
33 NUMBER_SINT = 0x5,
34 NUMBER_SRGB = 0x6,
35 NUMBER_FLOAT = 0x7,
38 SWAP_STD = 0x0,
39 SWAP_ALT = 0x1,
[all …]

12