Lines Matching +full:0 +full:x7c000000
187 i = 0; in show_stacktrace()
189 if (i && ((i % (64 / field)) == 0)) { in show_stacktrace()
203 pr_cont(" %0*lx", field, stackdata); in show_stacktrace()
217 regs.regs[31] = 0; in show_stack()
218 regs.cp0_epc = 0; in show_stack()
222 regs.regs[31] = 0; in show_stack()
277 for (i = 0; i < 32; ) { in __show_regs()
278 if ((i % 4) == 0) in __show_regs()
280 if (i == 0) in __show_regs()
281 pr_cont(" %0*lx", field, 0UL); in __show_regs()
285 pr_cont(" %0*lx", field, regs->regs[i]); in __show_regs()
288 if ((i % 4) == 0) in __show_regs()
293 printk("Acx : %0*lx\n", field, regs->acx); in __show_regs()
296 printk("Hi : %0*lx\n", field, regs->hi); in __show_regs()
297 printk("Lo : %0*lx\n", field, regs->lo); in __show_regs()
303 printk("epc : %0*lx %pS\n", field, regs->cp0_epc, in __show_regs()
305 printk("ra : %0*lx %pS\n", field, regs->regs[31], in __show_regs()
357 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); in __show_regs()
378 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", in show_registers()
386 printk("*HwTLS: %0*lx\n", field, tls); in show_registers()
403 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr, in die()
405 sig = 0; in die()
486 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", in do_be()
489 if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr, in do_be()
504 #define OPCODE 0xfc000000
505 #define BASE 0x03e00000
506 #define RT 0x001f0000
507 #define OFFSET 0x0000ffff
508 #define LL 0xc0000000
509 #define SC 0xe0000000
510 #define SPEC0 0x00000000
511 #define SPEC3 0x7c000000
512 #define RD 0x0000f800
513 #define FUNC 0x0000003f
514 #define SYNC 0x0000000f
515 #define RDHWR 0x0000003b
518 #define MM_POOL32A_FUNC 0xfc00ffff
519 #define MM_RDHWR 0x00006b3c
520 #define MM_RS 0x001f0000
521 #define MM_RT 0x03e00000
558 ll_bit = 0; in simulate_ll()
566 return 0; in simulate_ll()
594 if (ll_bit == 0 || ll_task != current) { in simulate_sc()
595 regs->regs[reg] = 0; in simulate_sc()
597 return 0; in simulate_sc()
607 return 0; in simulate_sc()
621 1, regs, 0); in simulate_llsc()
626 1, regs, 0); in simulate_llsc()
642 1, regs, 0); in simulate_rdhwr()
646 return 0; in simulate_rdhwr()
650 return 0; in simulate_rdhwr()
653 return 0; in simulate_rdhwr()
663 return 0; in simulate_rdhwr()
666 return 0; in simulate_rdhwr()
679 return 0; in simulate_rdhwr_normal()
692 return 0; in simulate_rdhwr_mm()
703 1, regs, 0); in simulate_sync()
704 return 0; in simulate_sync()
716 #define LWC2 0xc8000000
718 #define CSR_OPCODE2 0x00000118
719 #define CSR_OPCODE2_MASK 0x000007ff
721 #define CSR_FUNC_CPUCFG 0x8
735 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0); in simulate_loongson3_cpucfg()
746 return 0; in simulate_loongson3_cpucfg()
797 case 0: in process_fpemu_return()
798 return 0; in process_fpemu_return()
870 return 0; in simulate_fp()
883 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr, in do_fpe()
938 if (mt_fpemul_threshold > 0 && in mt_ase_fp_affinity()
1037 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; in do_bp()
1041 if (__get_inst16(&instr[0], (u16 *)epc, user)) in do_bp()
1046 bcode = (instr[0] >> 5) & 0x3f; in do_bp()
1047 } else if (mm_insn_16bit(instr[0])) { in do_bp()
1049 bcode = instr[0] & 0xf; in do_bp()
1054 opcode = (instr[0] << 16) | instr[1]; in do_bp()
1118 u32 opcode, tcode = 0; in do_tr()
1125 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; in do_tr()
1127 if (__get_inst16(&instr[0], (u16 *)(epc + 0), user) || in do_tr()
1130 opcode = (instr[0] << 16) | instr[1]; in do_tr()
1142 do_trap_or_bp(regs, tcode, 0, "Trap"); in do_tr()
1159 unsigned int opcode = 0; in do_ri()
1168 likely(get_user(opcode, epc) >= 0)) { in do_ri()
1169 unsigned long fcr31 = 0; in do_ri()
1173 case 0: in do_ri()
1189 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; in do_ri()
1191 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr, in do_ri()
1197 if (unlikely(compute_return_epc(regs) < 0)) in do_ri()
1201 if (unlikely(get_user(opcode, epc) < 0)) in do_ri()
1204 if (!cpu_has_llsc && status < 0) in do_ri()
1207 if (status < 0) in do_ri()
1210 if (status < 0) in do_ri()
1213 if (status < 0) in do_ri()
1217 if (status < 0) in do_ri()
1221 unsigned short mmop[2] = { 0 }; in do_ri()
1223 if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0)) in do_ri()
1225 if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0)) in do_ri()
1227 opcode = mmop[0]; in do_ri()
1230 if (status < 0) in do_ri()
1234 if (status < 0) in do_ri()
1237 if (unlikely(status > 0)) { in do_ri()
1248 * No lock; only written during early bootup by CPU 0.
1344 err = own_fpu_inatomic(0); in enable_restore_fp_context()
1392 return 0; in enable_restore_fp_context()
1420 case 0: in do_cpu()
1424 opcode = 0; in do_cpu()
1427 if (unlikely(compute_return_epc(regs) < 0)) in do_cpu()
1431 if (unlikely(get_user(opcode, epc) < 0)) in do_cpu()
1434 if (!cpu_has_llsc && status < 0) in do_cpu()
1438 if (status < 0) in do_cpu()
1441 if (unlikely(status > 0)) { in do_cpu()
1473 err = enable_restore_fp_context(0); in do_cpu()
1478 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0, in do_cpu()
1514 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; in do_msa_fpe()
1515 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0, in do_msa_fpe()
1621 case 0: in do_mt()
1667 (regs->cp0_cause & 0x7f) >> 2); in do_reserved()
1673 l1parity = 0; in nol1parity()
1680 l2parity = 0; in nol2parity()
1691 #define ERRCTL_PE 0x80000000 in parity_protection_init()
1692 #define ERRCTL_L2P 0x00800000 in parity_protection_init()
1723 l1parity = l2parity = 0; in parity_protection_init()
1816 write_c0_errctl(0x80000000); in parity_protection_init()
1820 str_enabled_disabled(read_c0_errctl() & 0x80000000)); in parity_protection_init()
1841 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); in cache_parity_error()
1849 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) { in cache_parity_error()
1869 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); in cache_parity_error()
1873 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); in cache_parity_error()
1876 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); in cache_parity_error()
1889 (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) || in do_ftlb()
1890 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) { in do_ftlb()
1891 pr_err("FTLB error exception, cp0_errctl=0x%08x:\n", in do_ftlb()
1893 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); in do_ftlb()
1897 if ((reg_val & 0xc0000000) == 0xc0000000) { in do_ftlb()
1920 case 0x08: in do_gsexc()
1955 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); in ejtag_exception_handler()
1956 if (debug & 0x80000000) { in ejtag_exception_handler()
1974 #if 0 in ejtag_exception_handler()
1976 write_c0_debug(debug | 0x100); in ejtag_exception_handler()
1982 * No lock; only written during early bootup by CPU 0.
1996 raw_notifier_call_chain(&nmi_chain, 0, regs); in nmi_exception_handler()
2017 if (smp_processor_id() == 0) in reserve_exception_space()
2034 if (!(handler & 0x1)) in set_except_vector()
2039 if (n == 0 && cpu_has_divec) { in set_except_vector()
2045 u32 *buf = (u32 *)(ebase + 0x200); in set_except_vector()
2046 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { in set_except_vector()
2054 local_flush_icache_range(ebase + 0x200, (unsigned long)buf); in set_except_vector()
2087 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); in set_vi_handler()
2091 board_bind_eic_interrupt(n, 0); in set_vi_handler()
2095 change_c0_srsmap(0xf << n*4, 0 << n*4); in set_vi_handler()
2221 change_c0_intctl(0x3e0, VECTORSPACING); in configure_exception_vector()
2265 cpu_data[cpu].asid_cache = 0; in per_cpu_trap_init()
2332 vec_size = 0x400; in trap_init()
2335 vec_size = 0x200 + VECTORSPACING*64; in trap_init()
2341 panic("%s: Failed to allocate %lu bytes align=0x%x\n", in trap_init()
2355 if (!IS_ENABLED(CONFIG_EVA) && ebase_pa < 0x20000000) in trap_init()
2359 if (ebase_pa >= 0x20000000) in trap_init()
2383 set_handler(0x180, &except_vec3_generic, 0x80); in trap_init()
2388 for (i = 0; i <= 31; i++) in trap_init()
2409 for (i = 0; i < nvec; i++) in trap_init()
2413 set_handler(0x200, &except_vec4, 0x8); in trap_init()
2493 set_handler(0x180, &except_vec3_r4000, 0x100); in trap_init()
2495 set_handler(0x180, &except_vec3_generic, 0x80); in trap_init()
2497 set_handler(0x080, &except_vec3_generic, 0x80); in trap_init()
2503 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ in trap_init()