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/freebsd/sys/contrib/device-tree/Bindings/nvmem/
H A Dqcom,qfprom.yaml93 reg = <0 0x00784000 0 0x8ff>,
94 <0 0x00780000 0 0x7a0>,
95 <0 0x00782000 0 0x100>,
96 <0 0x00786000 0 0x1fff>;
105 reg = <0x25b 0x1>;
118 reg = <0 0x00784000 0 0x8ff>;
123 reg = <0x1eb 0x1>;
/freebsd/sys/dev/mgb/
H A Dif_mgb.h33 #define MGB_MICROCHIP_VENDOR_ID 0x1055
34 #define MGB_LAN7430_DEVICE_ID 0x7430
35 #define MGB_LAN7431_DEVICE_ID 0x7431
40 #define MGB_BAR 0 /* PCI Base Address */
43 #define MGB_HW_CFG 0x10 /** H/W Configuration Register **/
44 #define MGB_LITE_RESET 0x2
47 #define MGB_MAC_CR 0x0100 /** MAC Crontrol Register **/
48 #define MGB_MAC_ADD_ENBL 0x1000 /* Automatic Duplex Detection */
49 #define MGB_MAC_ASD_ENBL 0x0800 /* Automatic Speed Detection */
51 #define MGB_MAC_ADDR_BASE_L 0x11C /** MAC address lower 4 bytes (read) register **/
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H A Dif_mgb.c211 #if 0 /* MIIBUS_DEBUG */
241 #if 0 /* Not yet implemented IFLIB methods */
315 #if 0 /* UNUSED_CTX */
349 scctx->isc_txqsizes[0] = sizeof(struct mgb_ring_desc) * in mgb_attach_pre()
350 scctx->isc_ntxd[0]; in mgb_attach_pre()
351 scctx->isc_rxqsizes[0] = sizeof(struct mgb_ring_desc) * in mgb_attach_pre()
352 scctx->isc_nrxd[0]; in mgb_attach_pre()
364 scctx->isc_tx_csum_flags = 0; in mgb_attach_pre()
365 scctx->isc_capabilities = scctx->isc_capenable = 0; in mgb_attach_pre()
366 #if 0 in mgb_attach_pre()
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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
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H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
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H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
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H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
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/freebsd/sys/x86/cpufreq/
H A Dpowernow.c54 #define PN7_TYPE 0
58 #define A0_ERRATA 0x1 /* Bugs for the rev. A0 of Athlon (K7):
61 #define PENDING_STUCK 0x2 /* With some buggy chipset and some newer AMD64
67 #define PSB_START 0
68 #define PSB_STEP 0x10
71 #define PSB_OFF 0
93 #define MSR_AMDK7_FIDVID_CTL 0xc0010041
94 #define MSR_AMDK7_FIDVID_STATUS 0xc0010042
98 #define PN7_CTR_FID(x) ((x) & 0x1f)
99 #define PN7_CTR_VID(x) (((x) & 0x1f) << 8)
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/freebsd/sys/riscv/include/
H A Dencoding.h8 #define MATCH_BEQ 0x63
9 #define MASK_BEQ 0x707f
10 #define MATCH_BNE 0x1063
11 #define MASK_BNE 0x707f
12 #define MATCH_BLT 0x4063
13 #define MASK_BLT 0x707f
14 #define MATCH_BGE 0x5063
15 #define MASK_BGE 0x707f
16 #define MATCH_BLTU 0x6063
17 #define MASK_BLTU 0x707f
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/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dscorpion_reg_map.h77 volatile char pad__0[0x8]; /* 0x0 - 0x8 */
78 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
79 volatile char pad__1[0x8]; /* 0xc - 0x14 */
80 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
81 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
82 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
83 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
84 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
85 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
86 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
[all …]
H A Dosprey_reg_map.h86 volatile char pad__0[0x8]; /* 0x0 - 0x8 */
87 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
88 volatile char pad__1[0x8]; /* 0xc - 0x14 */
89 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
90 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
91 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
92 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
93 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
94 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
95 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSystemOperands.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
30 // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3.
31 // Privilege Mode: User = 0, System = 1 or Machine = 3.
37 // bits<6> Number = op{5 - 0};
39 bit isRV32Only = 0;
78 def SysRegFFLAGS : SysReg<"fflags", 0x001>;
79 def SysRegFRM : SysReg<"frm", 0x002>;
80 def SysRegFCSR : SysReg<"fcsr", 0x003>;
85 def CYCLE : SysReg<"cycle", 0xC00>;
86 def TIME : SysReg<"time", 0xC01>;
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/freebsd/sys/dev/mlx5/
H A Dmlx5_ifc.h32 MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0,
33 MLX5_EVENT_TYPE_COMP = 0x0,
34 MLX5_EVENT_TYPE_PATH_MIG = 0x1,
35 MLX5_EVENT_TYPE_COMM_EST = 0x2,
36 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3,
37 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
38 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
39 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
40 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d,
41 MLX5_EVENT_TYPE_CQ_ERROR = 0x4,
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsc7180.dtsi66 #clock-cells = <0>;
72 #clock-cells = <0>;
78 #size-cells = <0>;
80 CPU0: cpu@0 {
83 reg = <0x0 0x0>;
84 clocks = <&cpufreq_hw 0>;
95 qcom,freq-domain = <&cpufreq_hw 0>;
112 reg = <0x0 0x100>;
113 clocks = <&cpufreq_hw 0>;
124 qcom,freq-domain = <&cpufreq_hw 0>;
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/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8186.dtsi329 #size-cells = <0>;
367 cpu0: cpu@0 {
370 reg = <0x000>;
394 reg = <0x100>;
418 reg = <0x200>;
442 reg = <0x300>;
466 reg = <0x400>;
490 reg = <0x500>;
514 reg = <0x600>;
538 reg = <0x700>;
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H A Dmt8195.dtsi51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x000>;
58 performance-domains = <&performance 0>;
75 reg = <0x100>;
77 performance-domains = <&performance 0>;
94 reg = <0x200>;
96 performance-domains = <&performance 0>;
113 reg = <0x300>;
115 performance-domains = <&performance 0>;
[all …]
/freebsd/sys/dev/mrsas/
H A Dmrsas.h78 #define MRSAS_TBOLT 0x005b
79 #define MRSAS_INVADER 0x005d
80 #define MRSAS_FURY 0x005f
81 #define MRSAS_INTRUDER 0x00ce
82 #define MRSAS_INTRUDER_24 0x00cf
83 #define MRSAS_CUTLASS_52 0x0052
84 #define MRSAS_CUTLASS_53 0x0053
86 #define MRSAS_VENTURA 0x0014
87 #define MRSAS_CRUSADER 0x0015
88 #define MRSAS_HARPOON 0x0016
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/freebsd/contrib/ofed/opensm/opensm/
H A Dosm_torus.c64 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
119 enum endpt_type { UNKNOWN = 0, SRCSINK, PASSTHRU };
189 * used as follows, assuming 0 <= d < N:
195 * traversing a link from link.end[0] to link.end[1] is always in the positive
267 * A torus dimension has coordinate values 0, 1, ..., radix - 1.
270 * radix - 1 and 0. The following specify the dateline location
273 * E.g. if the shared switch is at 0,0,0, the following are all
316 #define X_MESH (1U << 0)
347 for (s = 0; s < f->switch_cnt; s++) { in teardown_fabric()
352 for (p = 0; p < sw->port_cnt; p++) { in teardown_fabric()
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/freebsd/tools/tools/cxgbtool/
H A Dreg_defs_t3.c8 { "SG_CONTROL", 0x0, 0 },
22 { "GlobalEnable", 0, 1 },
23 { "SG_KDOORBELL", 0x4, 0 },
25 { "EgrCntx", 0, 16 },
26 { "SG_GTS", 0x8, 0 },
29 { "NewIndex", 0, 16 },
30 { "SG_CONTEXT_CMD", 0xc, 0 },
38 { "Context", 0, 16 },
39 { "SG_CONTEXT_DATA0", 0x10, 0 },
40 { "SG_CONTEXT_DATA1", 0x14, 0 },
[all …]
H A Dreg_defs_t3b.c7 { "SG_CONTROL", 0x0, 0 },
26 { "GlobalEnable", 0, 1 },
27 { "SG_KDOORBELL", 0x4, 0 },
29 { "EgrCntx", 0, 16 },
30 { "SG_GTS", 0x8, 0 },
33 { "NewIndex", 0, 16 },
34 { "SG_CONTEXT_CMD", 0xc, 0 },
42 { "Context", 0, 16 },
43 { "SG_CONTEXT_DATA0", 0x10, 0 },
44 { "SG_CONTEXT_DATA1", 0x14, 0 },
[all …]
H A Dreg_defs_t3c.c7 { "SG_CONTROL", 0x0, 0 },
29 { "GlobalEnable", 0, 1 },
30 { "SG_KDOORBELL", 0x4, 0 },
32 { "EgrCntx", 0, 16 },
33 { "SG_GTS", 0x8, 0 },
36 { "NewIndex", 0, 16 },
37 { "SG_CONTEXT_CMD", 0xc, 0 },
45 { "Context", 0, 16 },
46 { "SG_CONTEXT_DATA0", 0x10, 0 },
47 { "SG_CONTEXT_DATA1", 0x14, 0 },
[all …]
/freebsd/sys/dev/cxgb/common/
H A Dcxgb_regs.h33 #define SGE3_BASE_ADDR 0x0
35 #define A_SG_CONTROL 0x0
82 #define M_USERSPACESIZE 0x1f
87 #define M_HOSTPAGESIZE 0x7
100 #define M_PKTSHIFT 0x7
124 #define S_GLOBALENABLE 0
128 #define A_SG_KDOORBELL 0x4
134 #define S_EGRCNTX 0
135 #define M_EGRCNTX 0xffff
139 #define A_SG_GTS 0x8
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