Lines Matching +full:0 +full:x7a0
33 #define MGB_MICROCHIP_VENDOR_ID 0x1055
34 #define MGB_LAN7430_DEVICE_ID 0x7430
35 #define MGB_LAN7431_DEVICE_ID 0x7431
40 #define MGB_BAR 0 /* PCI Base Address */
43 #define MGB_HW_CFG 0x10 /** H/W Configuration Register **/
44 #define MGB_LITE_RESET 0x2
47 #define MGB_MAC_CR 0x0100 /** MAC Crontrol Register **/
48 #define MGB_MAC_ADD_ENBL 0x1000 /* Automatic Duplex Detection */
49 #define MGB_MAC_ASD_ENBL 0x0800 /* Automatic Speed Detection */
51 #define MGB_MAC_ADDR_BASE_L 0x11C /** MAC address lower 4 bytes (read) register **/
52 #define MGB_MAC_ADDR_BASE_H 0x118 /** MAC address upper 2 bytes (read) register **/
54 #define MGB_MAC_TX 0x0104
55 #define MGB_MAC_RX 0x0108
56 #define MGB_MAC_ENBL (1 << 0)
60 #define MGB_MAC_STAT_RX_FCS_ERR_CNT 0x1200
61 #define MGB_MAC_STAT_RX_ALIGN_ERR_CNT 0x1204
62 #define MGB_MAC_STAT_RX_FRAG_ERR_CNT 0x1208
63 #define MGB_MAC_STAT_RX_JABBER_ERR_CNT 0x120C
64 #define MGB_MAC_STAT_RX_UNDER_ERR_CNT 0x1210
65 #define MGB_MAC_STAT_RX_OVER_ERR_CNT 0x1214
66 #define MGB_MAC_STAT_RX_DROPPED_CNT 0x1218
67 #define MGB_MAC_STAT_RX_BROADCAST_CNT1 0x1220
68 #define MGB_MAC_STAT_RX_BROADCAST_CNT 0x122C
69 #define MGB_MAC_STAT_RX_FRAME_CNT 0x1254
70 #define MGB_MAC_STAT_RX_DROPPED_CNT 0x1218
71 #define MGB_MAC_STAT_RX_BROADCAST_CNT1 0x1220
72 #define MGB_MAC_STAT_RX_BROADCAST_CNT 0x122C
73 #define MGB_MAC_STAT_RX_FRAME_CNT 0x1254
77 #define MGB_RFE_CTL 0x508
84 #define MGB_PMT_CTL 0x14 /** Power Management Control Register **/
85 #define MGB_PHY_RESET 0x10
86 #define MGB_PHY_READY 0x80
89 #define MGB_FCT_TX_CTL 0xC4
90 #define MGB_FCT_RX_CTL 0xAC
96 #define MGB_DMAC_CMD 0xC0C
99 #define MGB_DMAC_RX_START 0
103 #define MGB_DMAC_CMD_STOP( _s, _ch) MGB_DMAC_CMD_VAL(_s, 0, _ch)
105 (((_start) ? 2 : 0) | ((_stop) ? 1 : 0))
106 #define MGB_DMAC_STATE_INITIAL MGB_DMAC_STATE(0, 0)
107 #define MGB_DMAC_STATE_STARTED MGB_DMAC_STATE(1, 0)
109 #define MGB_DMAC_STATE_STOPPED MGB_DMAC_STATE(0, 1)
117 #define MGB_DMAC_INTR_STS 0xC10
118 #define MGB_DMAC_INTR_ENBL_SET 0xC14
119 #define MGB_DMAC_INTR_ENBL_CLR 0xC18
140 #define MGB_DMA_TX_CONFIG0(_channel) MGB_DMA_REG(0x0D40, _channel)
141 #define MGB_DMA_TX_CONFIG1(_channel) MGB_DMA_REG(0x0D44, _channel)
142 #define MGB_DMA_TX_BASE_H(_channel) MGB_DMA_REG(0x0D48, _channel)
143 #define MGB_DMA_TX_BASE_L(_channel) MGB_DMA_REG(0x0D4C, _channel)
144 #define MGB_DMA_TX_HEAD_WB_H(_channel) MGB_DMA_REG(0x0D50, _channel) /* head Writeback */
145 #define MGB_DMA_TX_HEAD_WB_L(_channel) MGB_DMA_REG(0x0D54, _channel)
146 #define MGB_DMA_TX_HEAD(_channel) MGB_DMA_REG(0x0D58, _channel)
147 #define MGB_DMA_TX_TAIL(_channel) MGB_DMA_REG(0x0D5C, _channel)
149 #define MGB_DMA_RX_CONFIG0(_channel) MGB_DMA_REG(0x0C40, _channel)
150 #define MGB_DMA_RX_CONFIG1(_channel) MGB_DMA_REG(0x0C44, _channel)
151 #define MGB_DMA_RX_BASE_H(_channel) MGB_DMA_REG(0x0C48, _channel)
152 #define MGB_DMA_RX_BASE_L(_channel) MGB_DMA_REG(0x0C4C, _channel)
153 #define MGB_DMA_RX_HEAD_WB_H(_channel) MGB_DMA_REG(0x0C50, _channel) /* head Writeback */
154 #define MGB_DMA_RX_HEAD_WB_L(_channel) MGB_DMA_REG(0x0C54, _channel)
155 #define MGB_DMA_RX_HEAD(_channel) MGB_DMA_REG(0x0C58, _channel)
156 #define MGB_DMA_RX_TAIL(_channel) MGB_DMA_REG(0x0C5C, _channel)
158 #define MGB_DMA_RING_LEN_MASK 0xFFFF
159 #define MGB_DMA_IOC_ENBL 0x10000000
160 #define MGB_DMA_HEAD_WB_LS_ENBL 0x20000000
162 #define MGB_DMA_RING_PAD_MASK 0x03000000
163 #define MGB_DMA_RING_PAD_0 0x00000000
164 #define MGB_DMA_RING_PAD_2 0x02000000
173 #define MGB_DESC_CTL_BUFLEN_MASK (0x0000FFFF)
174 #define MGB_DESC_STS_BUFLEN_MASK (0x00003FFF)
175 #define MGB_DESC_FRAME_LEN_MASK (0x3FFF0000)
179 #define MGB_NEXT_RING_IDX(_idx) (((_idx) == MGB_DMA_RING_SIZE - 1) ? 0 : ((_idx) + 1))
180 #define MGB_PREV_RING_IDX(_idx) (((_idx) == 0) ? (MGB_DMA_RING_SIZE - 1) : ((_idx) - 1))
186 #define MGB_MII_ACCESS 0x120
187 #define MGB_MII_DATA 0x124
188 #define MGB_MII_PHY_ADDR_MASK 0x1F
190 #define MGB_MII_REG_ADDR_MASK 0x1F
192 #define MGB_MII_READ 0x0
193 #define MGB_MII_WRITE 0x2
194 #define MGB_MII_BUSY 0x1
197 #define MGB_INTR_STS 0x780
198 #define MGB_INTR_SET 0x784 /* This triggers a particular interrupt */
199 #define MGB_INTR_ENBL_SET 0x788
200 #define MGB_INTR_STS_ANY (0x1)
202 #define MGB_INTR_STS_RX_ANY (0xF << 24)
204 #define MGB_INTR_STS_TX_ANY (0xF << 16)
206 #define MGB_INTR_ENBL_CLR 0x78C
208 #define MGB_INTR_VEC_ENBL_SET 0x794
209 #define MGB_INTR_VEC_ENBL_CLR 0x798
210 #define MGB_INTR_VEC_ENBL_AUTO_CLR 0x79C
211 #define MGB_INTR_VEC_RX_MAP 0x7A0
212 #define MGB_INTR_VEC_TX_MAP 0x7A4
213 #define MGB_INTR_VEC_OTHER_MAP 0x7A8
218 #define MGB_STS_OK ( 0 )
248 #define CSR_TRANSLATE_ADDR_LOW32(addr) ((uint64_t) (addr) & 0xFFFFFFFF)
276 #if 0