mlx5_core: fix panic on sriov enablement

Align the code of fdb steering with flow steering core
and add missing parts in namespace initialization and
in prio logic

PR: 281714
Sponsored by: NVidia n

mlx5_core: fix panic on sriov enablement

Align the code of fdb steering with flow steering core
and add missing parts in namespace initialization and
in prio logic

PR: 281714
Sponsored by: NVidia networking

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mlx5en: add IPSEC_OFFLOAD support

Right now, only IPv4 transport mode, with aes-gcm ESP, is supported.
Driver also cooperates with NAT-T, and obeys socket policies, which
makes IKEd like StrongSwan

mlx5en: add IPSEC_OFFLOAD support

Right now, only IPv4 transport mode, with aes-gcm ESP, is supported.
Driver also cooperates with NAT-T, and obeys socket policies, which
makes IKEd like StrongSwan working.

Sponsored by: NVIDIA networking

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mlx5: Introduce new destination type TABLE_TYPE

This new destination type supports flow transition between different
table types, e.g. from NIC_RX to RDMA_RX or from RDMA_TX to NIC_TX.

In addition

mlx5: Introduce new destination type TABLE_TYPE

This new destination type supports flow transition between different
table types, e.g. from NIC_RX to RDMA_RX or from RDMA_TX to NIC_TX.

In addition add driver support to be able to query the capability for
this new destination type.

Signed-off-by: Patrisious Haddad <phaddad@nvidia.com>
Sponsored by: NVidia networking
MFC after: 1 week

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mlx5: add fs_counters

Signed-off-by: Raed Salem <raeds@nvidia.com>
Sponsored by: NVidia networking
MFC after: 1 week

mlx5: Add packet reformat support to flow rules

Allow attaching a packet reformat action to a flow rule.

Signed-off-by: Mark Bloch <mbloch@nvidia.com>
Sponsored by: NVidia networking
MFC after: 1 w

mlx5: Add packet reformat support to flow rules

Allow attaching a packet reformat action to a flow rule.

Signed-off-by: Mark Bloch <mbloch@nvidia.com>
Sponsored by: NVidia networking
MFC after: 1 week

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mlx5: Add modify header support to flow rules

Allow attaching a modify header to a flow rule.

Signed-off-by: Mark Bloch <mbloch@nvidia.com>
Sponsored by: NVidia networking
MFC after: 1 week

mlx5: Add packet reformat allocation support

Add support to allocating a packet reformat context.

Signed-off-by: Mark Bloch <mbloch@nvidia.com>
Sponsored by: NVidia networking
MFC after: 1 week

mlx5: Add modify header support

Add support to allocating a modify header context.

Signed-off-by: Mark Bloch <mbloch@nvidia.com>
Sponsored by: NVidia networking
MFC after: 1 week

sys: Remove $FreeBSD$: two-line .h pattern

Remove /^\s*\*\n \*\s+\$FreeBSD\$$\n/

mlx5: Implement diagostic counters as sysctl(8) nodes.

MFC after: 1 week
Sponsored by: NVIDIA Networking

mlx5en: Implement TLS RX support.

TLS RX support is modeled after TLS TX support. The basic structures and layouts
are almost identical, except that the send tag created filters RX traffic and
not T

mlx5en: Implement TLS RX support.

TLS RX support is modeled after TLS TX support. The basic structures and layouts
are almost identical, except that the send tag created filters RX traffic and
not TX traffic.

The TLS RX tag keeps track of past TLS records up to a certain limit,
approximately 1 Gbyte of TCP data. TLS records of same length are joined
into a single database record.

Regularly the HW is queried for TLS RX progress information. The TCP sequence
number gotten from the HW is then matches against the database of TLS TCP
sequence number records and lengths. If a match is found a static params WQE
is queued on the IQ and the hardware should immediately resume decrypting TLS
data until the next non-sequential TCP packet arrives.

Offloading TLS RX data is supported for untagged, prio-tagged, and
regular VLAN traffic.

MFC after: 1 week
Sponsored by: NVIDIA Networking

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mlx5: Implement mlx5_nic_vport_update_local_lb()

MFC after: 1 week
Sponsored by: NVIDIA Networking

mlx5: Implement flow steering helper functions for TCP sockets.

This change adds convenience functions to setup a flow steering rule based on
a TCP socket. The helper function gets all the address i

mlx5: Implement flow steering helper functions for TCP sockets.

This change adds convenience functions to setup a flow steering rule based on
a TCP socket. The helper function gets all the address information from the
socket and returns a steering rule, to be used with HW TLS RX offload.

MFC after: 1 week
Sponsored by: NVIDIA Networking

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mlx5/mlx5en: Add SQ remap support

Add support to map an SQ to a specific schedule queue using a
special WQE as performance enhancement.

SQ remap operation is handled by a privileged internal queue,

mlx5/mlx5en: Add SQ remap support

Add support to map an SQ to a specific schedule queue using a
special WQE as performance enhancement.

SQ remap operation is handled by a privileged internal queue, IQ,
and the mapping is enabled from one rate to another.

The transition from paced to non-paced should however always go
through FW.

MFC after: 1 week
Sponsored by: NVIDIA Networking

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mlx5: Properly define the reg_umr_sq networking offload capability bit.

MFC after: 1 week
Sponsored by: NVIDIA Networking

mlx5en: Make the receive packet indirection table, RQT, static instead of dynamic.

Allocate the RQT once, pointing all initial entries to the drop RQN.
When opening the channels simplify modify the

mlx5en: Make the receive packet indirection table, RQT, static instead of dynamic.

Allocate the RQT once, pointing all initial entries to the drop RQN.
When opening the channels simplify modify the RQT, directing all traffic
to the new RQNs. Similarly when closing the channels point all RQT entries
back to the so-called drop RQN.

MFC after: 1 week
Sponsored by: NVIDIA Networking

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ibcore: Kernel space update based on Linux 5.7-rc1.

Overview:

This is the first stage of a RDMA stack upgrade introducing kernel
changes only based on Linux 5.7-rc1.

This patch is based on about f

ibcore: Kernel space update based on Linux 5.7-rc1.

Overview:

This is the first stage of a RDMA stack upgrade introducing kernel
changes only based on Linux 5.7-rc1.

This patch is based on about four main areas of work:
- Update of the IB uobjects system:
- The memory holding so-called AH, CQ, PD, SRQ and UCONTEXT objects
is now managed by ibcore. This also require some changes in the
kernel verbs API. The updated verbs changes are typically about
initialize and deinitialize objects, and remove allocation and
free of memory.

- Update of the uverbs IOCTL framework:
- The parsing and handling of user-space commands has been
completely refactored to integrate with the updated IB uobjects
system.

- Various changes and updates to the generic uverbs interfaces in
device drivers including the new uAPI surface.

- The mlx5_ib_devx.c in mlx5ib and related mlx5 core changes.

Dependencies:

- The mlx4ib driver code has been updated with the minimum changes
needed.

- The mlx5ib driver code has been updated with the minimum changes
needed including DV support.

Compatibility:

- All user-space facing APIs are backwards compatible after this
change.

- All kernel-space facing RDMA APIs are backwards compatible after
this change, with exception of ib_create_ah() and ib_destroy_ah()
which takes a new flag.

- The "ib_device_ops" structure exist, but only contains the driver ID
and some structure sizes.

Differences from Linux:

- Infiniband drivers must use the INIT_IB_DEVICE_OPS() macro to set
the sizes needed for allocating various IB objects, when adding
IB device instances.

Security:

- PRIV_NET_RAW is needed to use raw ethernet transmit features.
- PRIV_DRIVER is needed to use other privileged operations.

Based on upstream Linux, Torvalds (5.7-rc1):
8632e9b5645bbc2331d21d892b0d6961c1a08429

MFC after: 1 week
Reviewed by: kib
Differential Revision: https://reviews.freebsd.org/D31149
Sponsored by: NVIDIA Networking

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mlx5: Fix for uninitialized "uid" field.

Make sure the "uid" field gets properly set when destroying DCT and QP
objects by making a copy of the field when creating such objects.

MFC after: 1 week
R

mlx5: Fix for uninitialized "uid" field.

Make sure the "uid" field gets properly set when destroying DCT and QP
objects by making a copy of the field when creating such objects.

MFC after: 1 week
Reviewed by: kib
Sponsored by: Mellanox Technologies // NVIDIA Networking

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mlx5en: Configure relaxed PCI read and write ordering for ethernet.

This may improve performance in some configurations.

MFC after: 1 week
Reviewed by: kib
Sponsored by: Mellanox Technologies // NV

mlx5en: Configure relaxed PCI read and write ordering for ethernet.

This may improve performance in some configurations.

MFC after: 1 week
Reviewed by: kib
Sponsored by: Mellanox Technologies // NVIDIA Networking

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mlx5: Add new timestamp mode bits.

These fields declare which timestamp mode is supported
by the device per RQ/SQ/QP.

In addition add the ts_format field to the select the mode
for RQ/SQ/QP.

Linux

mlx5: Add new timestamp mode bits.

These fields declare which timestamp mode is supported
by the device per RQ/SQ/QP.

In addition add the ts_format field to the select the mode
for RQ/SQ/QP.

Linux commit:
a6a217dddcd544f6b75f0e2a60b6e84c1d494b7e

MFC after: 1 week
Reviewed by: kib
Sponsored by: Mellanox Technologies // NVIDIA Networking

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mlx5: Fix PBMC register mapping

Import Linux commit 534b1204ca4694db1093b15cf3e79a99fcb6a6da

Add reserved mapping to cover all the register in order to avoid setting
arbitrary values to newer FW wh

mlx5: Fix PBMC register mapping

Import Linux commit 534b1204ca4694db1093b15cf3e79a99fcb6a6da

Add reserved mapping to cover all the register in order to avoid setting
arbitrary values to newer FW which implements the reserved fields.

Reviewed by: hselasky
Sponsored by: Mellanox Technologies // NVIDIA Networking
MFC after: 1 week

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mlx5: Fix PPLM register mapping

Import Linux commit ce28f0fd670ddffcd564ce7119bdefbaf08f02d3:
Add reserved mapping to cover all the register in order to avoid
setting arbitrary values to newer FW wh

mlx5: Fix PPLM register mapping

Import Linux commit ce28f0fd670ddffcd564ce7119bdefbaf08f02d3:
Add reserved mapping to cover all the register in order to avoid
setting arbitrary values to newer FW which implements the reserved
fields.

Taken from: https://patches.linaro.org/patch/417255/
Reviewed by: hselasky
Sponsored by: Mellanox Technologies // NVIDIA Networking
MFC after: 1 week

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Update user access region, UAR, APIs in the core in mlx5core.

This change include several changes as listed below all related to UAR.
UAR is a special PCI memory area where the so-called doorbell re

Update user access region, UAR, APIs in the core in mlx5core.

This change include several changes as listed below all related to UAR.
UAR is a special PCI memory area where the so-called doorbell register and
blue flame register live. Blue flame is a feature for sending small packets
more efficiently via a PCI memory page, instead of using PCI DMA.

- All structures and functions named xxx_uuars were renamed into xxx_bfreg.
- Remove partially implemented Blueflame support from mlx5en(4) and mlx5ib.
- Implement blue flame register allocator.
- Use blue flame register allocator in mlx5ib.
- A common UAR page is now allocated by the core to support doorbell register
writes for all of mlx5en and mlx5ib, instead of allocating one UAR per
sendqueue.
- Add support for DEVX query UAR.
- Add support for 4K UAR for libmlx5.

Linux commits:
7c043e908a74ae0a935037cdd984d0cb89b2b970
2f5ff26478adaff5ed9b7ad4079d6a710b5f27e7
0b80c14f009758cefeed0edff4f9141957964211
30aa60b3bd12bd79b5324b7b595bd3446ab24b52
5fe9dec0d045437e48f112b8fa705197bd7bc3c0
0118717583cda6f4f36092853ad0345e8150b286
a6d51b68611e98f05042ada662aed5dbe3279c1e

MFC after: 1 week
Sponsored by: Mellanox Technologies // NVIDIA Networking

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mlx5_core: add mlx5_query_pddr().

And use it in mlx5_query_pddr_range_info() instead of direct register
access.

Sponsored by: Mellanox Technologies - Nvidia
MFC after: 1 week

mlx5_core: Import PDDR register definitions

PDDR (Port Diagnostics Database Register) is used to read the physical
layer debug database, which contains helpful troubleshooting information
regarding

mlx5_core: Import PDDR register definitions

PDDR (Port Diagnostics Database Register) is used to read the physical
layer debug database, which contains helpful troubleshooting information
regarding the state of the link.

PDDR register can only be queried when PCAM register reports it as
supported in its register mask. A new helper macro was added to
the MLX5_CAP_* infrastructure in order to access this mask.

Sponsored by: Mellanox Technologies - Nvidia
MFC after: 1 week

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