Lines Matching +full:0 +full:x7a0
211 #if 0 /* MIIBUS_DEBUG */
241 #if 0 /* Not yet implemented IFLIB methods */
315 #if 0 /* UNUSED_CTX */
349 scctx->isc_txqsizes[0] = sizeof(struct mgb_ring_desc) * in mgb_attach_pre()
350 scctx->isc_ntxd[0]; in mgb_attach_pre()
351 scctx->isc_rxqsizes[0] = sizeof(struct mgb_ring_desc) * in mgb_attach_pre()
352 scctx->isc_nrxd[0]; in mgb_attach_pre()
364 scctx->isc_tx_csum_flags = 0; in mgb_attach_pre()
365 scctx->isc_capabilities = scctx->isc_capenable = 0; in mgb_attach_pre()
366 #if 0 in mgb_attach_pre()
381 if (error != 0) { in mgb_attach_pre()
388 if (error != 0) in mgb_attach_pre()
392 if (error != 0) { in mgb_attach_pre()
412 if (error != 0) { in mgb_attach_pre()
445 /* Map all vectors to vector 0 (admin interrupts) by default. */ in mgb_attach_pre()
446 CSR_WRITE_REG(sc, MGB_INTR_VEC_RX_MAP, 0); in mgb_attach_pre()
447 CSR_WRITE_REG(sc, MGB_INTR_VEC_TX_MAP, 0); in mgb_attach_pre()
448 CSR_WRITE_REG(sc, MGB_INTR_VEC_OTHER_MAP, 0); in mgb_attach_pre()
450 return (0); in mgb_attach_pre()
467 return (0); in mgb_attach_post()
513 if (needs_reset != 0) in mgb_media_change()
526 if ((if_getflags(ifp) & IFF_UP) == 0) in mgb_media_status()
545 for (q = 0; q < ntxqsets; q++) { in mgb_tx_queues_alloc()
548 rdata->ring = (struct mgb_ring_desc *) vaddrs[q * ntxqs + 0]; in mgb_tx_queues_alloc()
549 rdata->ring_bus_addr = paddrs[q * ntxqs + 0]; in mgb_tx_queues_alloc()
555 return (0); in mgb_tx_queues_alloc()
569 for (q = 0; q < nrxqsets; q++) { in mgb_rx_queues_alloc()
572 rdata->ring = (struct mgb_ring_desc *) vaddrs[q * nrxqs + 0]; in mgb_rx_queues_alloc()
573 rdata->ring_bus_addr = paddrs[q * nrxqs + 0]; in mgb_rx_queues_alloc()
579 return (0); in mgb_rx_queues_alloc()
589 memset(&sc->rx_ring_data, 0, sizeof(struct mgb_ring_data)); in mgb_queues_free()
590 memset(&sc->tx_ring_data, 0, sizeof(struct mgb_ring_data)); in mgb_queues_free()
620 #if 0
625 int first_stat = 0x1200;
626 int last_stat = 0x12FC;
629 if (CSR_READ_REG(sc, i) != 0)
630 device_printf(sc->dev, "0x%04x: 0x%08x\n", i,
655 0x114,
656 0xA0,
657 0xC00,
658 0xC0C,
659 0xC10,
660 0xC14,
661 0xC60,
662 0xCA0,
663 0xCE0,
664 0xD20,
665 0x780,
666 0x788,
667 0x794,
668 0x7A0,
669 0x7A4,
670 0x780,
671 0xD58,
672 0xD5C,
673 0xD60,
674 0x0
676 i = 0;
679 device_printf(sc->dev, "%s at offset 0x%04x = 0x%08x\n",
683 for (i = 0; i < MGB_DMA_RING_SIZE; i++)
684 device_printf(sc->dev, "ring[%d].data0=0x%08x\n"
685 "ring[%d].data1=0x%08x\n"
686 "ring[%d].data2=0x%08x\n"
687 "ring[%d].data3=0x%08x\n",
693 CSR_WRITE_REG(sc, 0x24, 0xF); // DP_SEL & TX_RAM_0
694 for (i = 0; i < 128; i++) {
695 CSR_WRITE_REG(sc, 0x2C, i); // DP_ADDR
697 CSR_WRITE_REG(sc, 0x28, 0); // DP_CMD
699 while ((CSR_READ_REG(sc, 0x24) & 0x80000000) == 0) // DP_SEL & READY
703 CSR_READ_REG(sc, 0x30)); // DP_DATA
719 for (i = 0; i < scctx->isc_nrxqsets; i++) { in mgb_stop()
720 mgb_dmac_control(sc, MGB_DMAC_RX_START, 0, DMAC_STOP); in mgb_stop()
721 mgb_fct_control(sc, MGB_FCT_RX_CTL, 0, FCT_DISABLE); in mgb_stop()
723 for (i = 0; i < scctx->isc_ntxqsets; i++) { in mgb_stop()
724 mgb_dmac_control(sc, MGB_DMAC_TX_START, 0, DMAC_STOP); in mgb_stop()
725 mgb_fct_control(sc, MGB_FCT_TX_CTL, 0, FCT_DISABLE); in mgb_stop()
754 for (qidx = 0; qidx < scctx->isc_nrxqsets; qidx++) { in mgb_rxq_intr()
780 if ((intr_sts & MGB_INTR_STS_ANY) == 0) in mgb_admin_intr()
782 if ((intr_sts & MGB_INTR_STS_TEST) != 0) { in mgb_admin_intr()
787 if ((intr_sts & MGB_INTR_STS_RX_ANY) != 0) { in mgb_admin_intr()
788 for (qidx = 0; qidx < scctx->isc_nrxqsets; qidx++) { in mgb_admin_intr()
796 if ((intr_sts & MGB_INTR_STS_TX_ANY) != 0) { in mgb_admin_intr()
797 for (qidx = 0; qidx < scctx->isc_ntxqsets; qidx++) { in mgb_admin_intr()
830 * RIDs start at 1, and vector ids start at 0. in mgb_msix_intr_assign()
832 vectorid = 0; in mgb_msix_intr_assign()
834 IFLIB_INTR_ADMIN, mgb_admin_intr, sc, 0, "admin"); in mgb_msix_intr_assign()
841 for (i = 0; i < scctx->isc_nrxqsets; i++) { in mgb_msix_intr_assign()
856 for (i = 0; i < scctx->isc_ntxqsets; i++) { in mgb_msix_intr_assign()
862 return (0); in mgb_msix_intr_assign()
870 int i, dmac_enable = 0, intr_sts = 0, vec_en = 0; in mgb_intr_enable_all()
877 for (i = 0; i < scctx->isc_nrxqsets; i++) { in mgb_intr_enable_all()
917 return (0); in mgb_rx_queue_intr_enable()
932 return (0); in mgb_tx_queue_intr_enable()
948 for (i = 0; i < MGB_TIMEOUT; i++) { in mgb_intr_test()
968 KASSERT(ipi->ipi_qsidx == 0, in mgb_isc_txd_encap()
978 for (i = 0; i < nsegs; ++i) { in mgb_isc_txd_encap()
999 return (0); in mgb_isc_txd_encap()
1008 KASSERT(txqid == 0, ("tried to flush TX Channel %d.\n", txqid)); in mgb_isc_txd_flush()
1024 int processed = 0; in mgb_isc_txd_credits_update()
1033 KASSERT(txqid == 0, ("tried to credits_update TX Channel %d.\n", in mgb_isc_txd_credits_update()
1043 memset(txd, 0, sizeof(struct mgb_ring_desc)); in mgb_isc_txd_credits_update()
1056 int avail = 0; in mgb_isc_rxd_available()
1059 KASSERT(rxqid == 0, ("tried to check availability in RX Channel %d.\n", in mgb_isc_rxd_available()
1080 KASSERT(ri->iri_qsidx == 0, in mgb_isc_rxd_pkt_get()
1083 total_len = 0; in mgb_isc_rxd_pkt_get()
1094 if ((rxd.ctl & MGB_DESC_CTL_OWN) != 0) { in mgb_isc_rxd_pkt_get()
1100 if ((rxd.ctl & MGB_RX_DESC_CTL_FS) == 0) { in mgb_isc_rxd_pkt_get()
1108 if ((rxd.ctl & MGB_RX_DESC_CTL_LS) == 0) { in mgb_isc_rxd_pkt_get()
1114 ri->iri_frags[0].irf_flid = 0; in mgb_isc_rxd_pkt_get()
1115 ri->iri_frags[0].irf_idx = rdata->last_head; in mgb_isc_rxd_pkt_get()
1116 ri->iri_frags[0].irf_len = MGB_DESC_GET_FRAME_LEN(&rxd); in mgb_isc_rxd_pkt_get()
1117 total_len += ri->iri_frags[0].irf_len; in mgb_isc_rxd_pkt_get()
1125 return (0); in mgb_isc_rxd_pkt_get()
1143 KASSERT(iru->iru_qsidx == 0, in mgb_isc_rxd_refill()
1149 while (count > 0) { in mgb_isc_rxd_refill()
1153 rxd->sts = 0; in mgb_isc_rxd_refill()
1171 KASSERT(rxqid == 0, ("tried to flush RX Channel %d.\n", rxqid)); in mgb_isc_rxd_flush()
1187 id_rev = CSR_READ_REG(sc, 0); in mgb_test_bar()
1191 return (0); in mgb_test_bar()
1210 return (0); in mgb_alloc_regs()
1216 int error = 0; in mgb_release_regs()
1230 int ch, error = 0; in mgb_dma_init()
1234 for (ch = 0; ch < scctx->isc_nrxqsets; ch++) in mgb_dma_init()
1238 for (ch = 0; ch < scctx->isc_nrxqsets; ch++) in mgb_dma_init()
1250 int ring_config, error = 0; in mgb_dma_rx_ring_init()
1253 mgb_dmac_control(sc, MGB_DMAC_RX_START, 0, DMAC_RESET); in mgb_dma_rx_ring_init()
1258 if (rdata->ring_bus_addr == 0) { in mgb_dma_rx_ring_init()
1269 if (rdata->head_wb_bus_addr == 0) { in mgb_dma_rx_ring_init()
1294 if (error != 0) { in mgb_dma_rx_ring_init()
1299 if (error != 0) { in mgb_dma_rx_ring_init()
1304 if (error != 0) in mgb_dma_rx_ring_init()
1314 int ring_config, error = 0; in mgb_dma_tx_ring_init()
1335 if (rdata->ring_bus_addr == 0) { in mgb_dma_tx_ring_init()
1355 if (rdata->head_wb_bus_addr == 0) { in mgb_dma_tx_ring_init()
1365 KASSERT(rdata->last_head == 0, ("MGB_DMA_TX_HEAD was not reset.\n")); in mgb_dma_tx_ring_init()
1366 rdata->last_tail = 0; in mgb_dma_tx_ring_init()
1380 int error = 0; in mgb_dmac_control()
1386 error = mgb_wait_for_bits(sc, MGB_DMAC_CMD, 0, in mgb_dmac_control()
1396 if (error != 0) in mgb_dmac_control()
1421 return (mgb_wait_for_bits(sc, reg, 0, MGB_FCT_RESET(channel))); in mgb_fct_control()
1424 return (0); in mgb_fct_control()
1427 return (mgb_wait_for_bits(sc, reg, 0, MGB_FCT_ENBL(channel))); in mgb_fct_control()
1434 int err = 0; in mgb_hw_teardown()
1439 if ((err = mgb_wait_for_bits(sc, MGB_MAC_RX, MGB_MAC_DSBL, 0))) in mgb_hw_teardown()
1441 if ((err = mgb_wait_for_bits(sc, MGB_MAC_TX, MGB_MAC_DSBL, 0))) in mgb_hw_teardown()
1449 int error = 0; in mgb_hw_init()
1452 if (error != 0) in mgb_hw_init()
1458 if (error != 0) in mgb_hw_init()
1462 if (error != 0) in mgb_hw_init()
1474 return (mgb_wait_for_bits(sc, MGB_HW_CFG, 0, MGB_LITE_RESET)); in mgb_hw_reset()
1497 if (mgb_wait_for_bits(sc, MGB_PMT_CTL, 0, MGB_PHY_RESET) == in mgb_phy_reset()
1500 return (mgb_wait_for_bits(sc, MGB_PMT_CTL, MGB_PHY_READY, 0)); in mgb_phy_reset()
1508 return (mgb_wait_for_bits(sc, MGB_DMAC_CMD, 0, MGB_DMAC_RESET)); in mgb_dmac_reset()
1516 i = 0; in mgb_wait_for_bits()
1524 if ((val & set_bits) == set_bits && (val & clear_bits) == 0) in mgb_wait_for_bits()
1535 CSR_READ_REG_BYTES(sc, MGB_MAC_ADDR_BASE_L, &dest->octet[0], 4); in mgb_get_ethaddr()
1547 if (mgb_wait_for_bits(sc, MGB_MII_ACCESS, 0, MGB_MII_BUSY) == in mgb_miibus_readreg()
1554 if (mgb_wait_for_bits(sc, MGB_MII_ACCESS, 0, MGB_MII_BUSY) == in mgb_miibus_readreg()
1568 if (mgb_wait_for_bits(sc, MGB_MII_ACCESS, 0, MGB_MII_BUSY) == in mgb_miibus_writereg()
1576 if (mgb_wait_for_bits(sc, MGB_MII_ACCESS, 0, MGB_MII_BUSY) == in mgb_miibus_writereg()
1579 return (0); in mgb_miibus_writereg()