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/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8365.c18 /* 0E4E8SR 4/8/12/16 */
20 /* 0E2E4SR 2/4/6/8 */
23 MTK_DRV_GRP(2, 16, 0, 2, 2)
28 MTK_PIN_DRV_GRP(0, 0x710, 0, 2),
29 MTK_PIN_DRV_GRP(1, 0x710, 0, 2),
30 MTK_PIN_DRV_GRP(2, 0x710, 0, 2),
31 MTK_PIN_DRV_GRP(3, 0x710, 0, 2),
32 MTK_PIN_DRV_GRP(4, 0x710, 4, 2),
33 MTK_PIN_DRV_GRP(5, 0x710, 4, 2),
34 MTK_PIN_DRV_GRP(6, 0x710, 4, 2),
[all …]
/linux/drivers/clk/hisilicon/
H A Dclk-hi3660.c14 { HI3660_CLKIN_SYS, "clkin_sys", NULL, 0, 19200000, },
15 { HI3660_CLKIN_REF, "clkin_ref", NULL, 0, 32764, },
16 { HI3660_CLK_FLL_SRC, "clk_fll_src", NULL, 0, 128000000, },
17 { HI3660_CLK_PPLL0, "clk_ppll0", NULL, 0, 1600000000, },
18 { HI3660_CLK_PPLL1, "clk_ppll1", NULL, 0, 1866000000, },
19 { HI3660_CLK_PPLL2, "clk_ppll2", NULL, 0, 2880000000UL, },
20 { HI3660_CLK_PPLL3, "clk_ppll3", NULL, 0, 1290000000, },
21 { HI3660_CLK_SCPLL, "clk_scpll", NULL, 0, 245760000, },
22 { HI3660_PCLK, "pclk", NULL, 0, 20000000, },
23 { HI3660_CLK_UART0_DBG, "clk_uart0_dbg", NULL, 0, 19200000, },
[all …]
H A Dclk-hi3670.c17 { HI3670_CLKIN_SYS, "clkin_sys", NULL, 0, 19200000, },
18 { HI3670_CLKIN_REF, "clkin_ref", NULL, 0, 32764, },
19 { HI3670_CLK_FLL_SRC, "clk_fll_src", NULL, 0, 134400000, },
20 { HI3670_CLK_PPLL0, "clk_ppll0", NULL, 0, 1660000000, },
21 { HI3670_CLK_PPLL1, "clk_ppll1", NULL, 0, 1866000000, },
22 { HI3670_CLK_PPLL2, "clk_ppll2", NULL, 0, 1920000000, },
23 { HI3670_CLK_PPLL3, "clk_ppll3", NULL, 0, 1200000000, },
24 { HI3670_CLK_PPLL4, "clk_ppll4", NULL, 0, 900000000, },
25 { HI3670_CLK_PPLL6, "clk_ppll6", NULL, 0, 393216000, },
26 { HI3670_CLK_PPLL7, "clk_ppll7", NULL, 0, 1008000000, },
[all …]
/linux/include/dt-bindings/clock/
H A Dam4.h8 #define AM4_CLKCTRL_OFFSET 0x20
12 #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
14 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
17 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228
19 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
20 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
23 #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
25 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
26 #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
27 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
[all …]
H A Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
/linux/arch/sh/kernel/cpu/sh3/
H A Dsetup-sh7710.c19 UNUSED = 0,
33 INTC_VECT(DMAC1, 0x800), INTC_VECT(DMAC1, 0x820),
34 INTC_VECT(DMAC1, 0x840), INTC_VECT(DMAC1, 0x860),
35 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
36 INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
37 INTC_VECT(SCIF1, 0x900), INTC_VECT(SCIF1, 0x920),
38 INTC_VECT(SCIF1, 0x940), INTC_VECT(SCIF1, 0x960),
39 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0),
41 INTC_VECT(IPSEC, 0xbe0),
43 INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20),
[all …]
H A Dsetup-sh7705.c20 UNUSED = 0,
36 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
37 INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
38 INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
39 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
40 INTC_VECT(SCIF0, 0x8e0),
41 INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
42 INTC_VECT(SCIF2, 0x960),
43 INTC_VECT(ADC_ADI, 0x980),
44 INTC_VECT(USB, 0xa20), INTC_VECT(USB, 0xa40),
[all …]
H A Dsetup-sh770x.c24 UNUSED = 0,
36 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
37 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
38 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
39 INTC_VECT(RTC, 0x4c0),
40 INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500),
41 INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540),
42 INTC_VECT(WDT, 0x560),
43 INTC_VECT(REF, 0x580),
44 INTC_VECT(REF, 0x5a0),
[all …]
H A Dsetup-sh7720.c26 [0] = {
27 .start = 0xa413fec0,
28 .end = 0xa413fec0 + 0x28 - 1,
33 .start = evt2irq(0x480),
59 DEFINE_RES_MEM(0xa4430000, 0x100),
60 DEFINE_RES_IRQ(evt2irq(0xc00)),
65 .id = 0,
80 DEFINE_RES_MEM(0xa4438000, 0x100),
81 DEFINE_RES_IRQ(evt2irq(0xc20)),
95 [0] = {
[all …]
/linux/arch/arm/mach-omap2/
H A Domap-wakeupgen.h12 #define OMAP_WKUPGEN_BASE 0x48281000
14 #define OMAP_WKG_CONTROL_0 0x00
15 #define OMAP_WKG_ENB_A_0 0x10
16 #define OMAP_WKG_ENB_B_0 0x14
17 #define OMAP_WKG_ENB_C_0 0x18
18 #define OMAP_WKG_ENB_D_0 0x1c
19 #define OMAP_WKG_ENB_E_0 0x20
20 #define OMAP_WKG_ENB_A_1 0x410
21 #define OMAP_WKG_ENB_B_1 0x414
22 #define OMAP_WKG_ENB_C_1 0x418
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
/linux/drivers/watchdog/
H A Dnpcm_wdt.c16 #define NPCM_WTCR 0x1C
25 #define NPCM_WTR BIT(0) /* Reset counter */
30 * 170 msec: WTCLK=01 WTIS=00 VAL= 0x400
31 * 670 msec: WTCLK=01 WTIS=01 VAL= 0x410
32 * 1360 msec: WTCLK=10 WTIS=00 VAL= 0x800
33 * 2700 msec: WTCLK=01 WTIS=10 VAL= 0x420
34 * 5360 msec: WTCLK=10 WTIS=01 VAL= 0x810
35 * 10700 msec: WTCLK=01 WTIS=11 VAL= 0x430
36 * 21600 msec: WTCLK=10 WTIS=10 VAL= 0x820
37 * 43000 msec: WTCLK=11 WTIS=00 VAL= 0xC00
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hwio.h13 #define DISP_INTF_SEL 0x004
14 #define INTR_EN 0x010
15 #define INTR_STATUS 0x014
16 #define INTR_CLEAR 0x018
17 #define INTR2_EN 0x008
18 #define INTR2_STATUS 0x00c
19 #define SSPP_SPARE 0x028
20 #define INTR2_CLEAR 0x02c
21 #define HIST_INTR_EN 0x01c
22 #define HIST_INTR_STATUS 0x020
[all …]
/linux/sound/soc/sof/intel/
H A Datom.h15 #define IRAM_OFFSET 0x0C0000
17 #define DRAM_OFFSET 0x100000
19 #define SHIM_OFFSET 0x140000
20 #define SHIM_SIZE_BYT 0x100
21 #define SHIM_SIZE_CHT 0x118
22 #define MBOX_OFFSET 0x144000
23 #define MBOX_SIZE 0x1000
24 #define EXCEPT_OFFSET 0x800
25 #define EXCEPT_MAX_HDR_SIZE 0x400
28 #define DMAC0_OFFSET 0x098000
[all …]
/linux/drivers/net/ethernet/sfc/
H A Dio.h93 _efx_writeq(efx, value->u64[0], reg + 0); in efx_writeo()
96 _efx_writed(efx, value->u32[0], reg + 0); in efx_writeo()
113 _efx_writed(efx, value->u32[0], reg); in efx_writed()
123 value->u32[0] = _efx_readd(efx, reg + 0); in efx_reado()
138 value->u32[0] = _efx_readd(efx, reg); in efx_readd()
162 #define EFX_DEFAULT_VI_STRIDE 0x2000
163 #define EF100_DEFAULT_VI_STRIDE 0x10000
183 _efx_writeq(efx, value->u64[0], reg + 0); in _efx_writeo_page()
186 _efx_writed(efx, value->u32[0], reg + 0); in _efx_writeo_page()
195 BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \
[all …]
/linux/arch/sh/kernel/cpu/sh4/
H A Dsetup-sh7760.c17 UNUSED = 0,
44 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
45 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
46 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
47 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
48 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
49 INTC_VECT(DMAC, 0x6c0),
50 INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820),
51 INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860),
52 INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920),
[all …]
H A Dsetup-sh7750.c19 [0] = {
20 .start = 0xffc80000,
21 .end = 0xffc80000 + 0x58 - 1,
26 .start = evt2irq(0x480),
43 DEFINE_RES_MEM(0xffe00000, 0x20),
44 DEFINE_RES_IRQ(evt2irq(0x4e0)),
49 .id = 0,
63 DEFINE_RES_MEM(0xffe80000, 0x100),
64 DEFINE_RES_IRQ(evt2irq(0x700)),
82 DEFINE_RES_MEM(0xffd80000, 0x30),
[all …]
/linux/arch/arm64/include/asm/
H A Dvncr_mapping.h10 #define VNCR_VTTBR_EL2 0x020
11 #define VNCR_VTCR_EL2 0x040
12 #define VNCR_VMPIDR_EL2 0x050
13 #define VNCR_CNTVOFF_EL2 0x060
14 #define VNCR_HCR_EL2 0x078
15 #define VNCR_HSTR_EL2 0x080
16 #define VNCR_VPIDR_EL2 0x088
17 #define VNCR_TPIDR_EL2 0x090
18 #define VNCR_HCRX_EL2 0x0A0
19 #define VNCR_VNCR_EL2 0x0B0
[all …]
/linux/include/linux/soc/ixp4xx/
H A Dqmgr.h12 #define DEBUG_QMGR 0
25 #define QUEUE_WATERMARK_0_ENTRIES 0
35 #define QUEUE_IRQ_SRC_EMPTY 0
45 u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */
46 u32 stat1[4]; /* 0x400 - 0x40F */
47 u32 stat2[2]; /* 0x410 - 0x417 */
48 u32 statne_h; /* 0x418 - queue nearly empty */
49 u32 statf_h; /* 0x41C - queue full */
50 u32 irqsrc[4]; /* 0x420 - 0x42F IRC source */
51 u32 irqen[2]; /* 0x430 - 0x437 IRQ enabled */
[all …]
/linux/drivers/media/pci/cx18/
H A Dcx18-av-core.h32 CX18_AV_SVIDEO_LUMA1 = 0x10,
33 CX18_AV_SVIDEO_LUMA2 = 0x20,
34 CX18_AV_SVIDEO_LUMA3 = 0x30,
35 CX18_AV_SVIDEO_LUMA4 = 0x40,
36 CX18_AV_SVIDEO_LUMA5 = 0x50,
37 CX18_AV_SVIDEO_LUMA6 = 0x60,
38 CX18_AV_SVIDEO_LUMA7 = 0x70,
39 CX18_AV_SVIDEO_LUMA8 = 0x80,
40 CX18_AV_SVIDEO_CHROMA4 = 0x400,
41 CX18_AV_SVIDEO_CHROMA5 = 0x500,
[all …]
/linux/arch/s390/boot/
H A Dhead_kdump.S11 #define DATAMOVER_ADDR 0x4000
12 #define COPY_PAGE_ADDR 0x6000
26 basr %r13,0
29 lg %r2,0(%r2) # already relocated:
32 lghi %r2,0 # Yes: Start kdump kernel
37 lg %r2,0x418(%r4) # Get kdump base
38 lg %r3,0x420(%r4) # Get kdump size
42 mvc 0(256,%r8),0(%r10) # Copy data mover code
45 mvc 0(256,%r8),0(%r10) # reserved mem
59 basr %r13,0 # Base
[all …]
/linux/drivers/net/ethernet/sfc/falcon/
H A Dio.h100 _ef4_writeq(efx, value->u64[0], reg + 0); in ef4_writeo()
103 _ef4_writed(efx, value->u32[0], reg + 0); in ef4_writeo()
124 __raw_writeq((__force u64)value->u64[0], membase + addr); in ef4_sram_writeq()
126 __raw_writel((__force u32)value->u32[0], membase + addr); in ef4_sram_writeq()
141 _ef4_writed(efx, value->u32[0], reg); in ef4_writed()
151 value->u32[0] = _ef4_readd(efx, reg + 0); in ef4_reado()
171 value->u64[0] = (__force __le64)__raw_readq(membase + addr); in ef4_sram_readq()
173 value->u32[0] = (__force __le32)__raw_readl(membase + addr); in ef4_sram_readq()
187 value->u32[0] = _ef4_readd(efx, reg); in ef4_readd()
209 #define EF4_VI_PAGE_SIZE 0x2000
[all …]
/linux/arch/sh/kernel/cpu/sh4a/
H A Dsetup-sh7366.c26 DEFINE_RES_MEM(0xffe00000, 0x100),
27 DEFINE_RES_IRQ(evt2irq(0xc00)),
32 .id = 0,
41 [0] = {
43 .start = 0x04470000,
44 .end = 0x04470017,
48 .start = evt2irq(0xe00),
49 .end = evt2irq(0xe60),
56 .id = 0, /* "i2c0" clock */
66 [0] = {
[all …]

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