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/linux/drivers/gpu/drm/amd/amdgpu/
H A Djpeg_v4_0_3.h27 #define regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 0x1bfff
28 #define regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x404d
29 #define regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x404e
30 #define regUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x404f
31 #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ab
32 #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40ac
33 #define regUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40a4
34 #define regUVD_LMI_JPEG_VMID_INTERNAL_OFFSET 0x40a6
35 #define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40b6
36 #define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40b7
[all …]
/linux/Documentation/devicetree/bindings/soc/ti/
H A Dti,j721e-system-controller.yaml48 "^mux-controller@[0-9a-f]+$":
53 "^clock-controller@[0-9a-f]+$":
59 "phy@[0-9a-f]+$":
65 "^chipid@[0-9a-f]+$":
84 reg = <0x00100000 0x1c000>;
91 reg = <0x00004080 0x50>;
95 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
96 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
97 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
98 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
[all …]
/linux/include/linux/mfd/wm831x/
H A Dcore.h25 #define WM831X_RESET_ID 0x00
26 #define WM831X_REVISION 0x01
27 #define WM831X_PARENT_ID 0x4000
28 #define WM831X_SYSVDD_CONTROL 0x4001
29 #define WM831X_THERMAL_MONITORING 0x4002
30 #define WM831X_POWER_STATE 0x4003
31 #define WM831X_WATCHDOG 0x4004
32 #define WM831X_ON_PIN_CONTROL 0x4005
33 #define WM831X_RESET_CONTROL 0x4006
34 #define WM831X_CONTROL_INTERFACE 0x4007
[all …]
/linux/drivers/net/ethernet/tehuti/
H A Dtn40_regs.h8 #define TN40_REGS_SIZE 0x10000
10 /* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */
11 #define TN40_REG_TXD_CFG1_0 0x4000
12 #define TN40_REG_TXD_CFG1_1 0x4004
13 #define TN40_REG_TXD_CFG1_2 0x4008
14 #define TN40_REG_TXD_CFG1_3 0x400C
16 #define TN40_REG_RXF_CFG1_0 0x4010
17 #define TN40_REG_RXF_CFG1_1 0x4014
18 #define TN40_REG_RXF_CFG1_2 0x4018
19 #define TN40_REG_RXF_CFG1_3 0x401C
[all …]
/linux/drivers/gpu/drm/radeon/reg_srcs/
H A Drv5151 rv515 0x6d40
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
/linux/drivers/crypto/tegra/
H A Dtegra-se.h20 #define SE_OWNERSHIP 0x14
21 #define SE_OWNERSHIP_UID(x) FIELD_GET(GENMASK(7, 0), x)
24 #define SE_STREAM_ID 0x90
26 #define SE_SHA_CFG 0x4004
27 #define SE_SHA_KEY_ADDR 0x4094
28 #define SE_SHA_KEY_DATA 0x4098
29 #define SE_SHA_KEYMANIFEST 0x409c
30 #define SE_SHA_CRYPTO_CFG 0x40a4
31 #define SE_SHA_KEY_DST 0x40a8
32 #define SE_SHA_SRC_KSLT 0x4180
[all …]
/linux/drivers/net/ethernet/agere/
H A Det131x.h53 #define LBCIF_DWORD0_GROUP 0xAC
54 #define LBCIF_DWORD1_GROUP 0xB0
57 #define LBCIF_ADDRESS_REGISTER 0xAC
58 #define LBCIF_DATA_REGISTER 0xB0
59 #define LBCIF_CONTROL_REGISTER 0xB1
60 #define LBCIF_STATUS_REGISTER 0xB2
63 #define LBCIF_CONTROL_SEQUENTIAL_READ 0x01
64 #define LBCIF_CONTROL_PAGE_WRITE 0x02
65 #define LBCIF_CONTROL_EEPROM_RELOAD 0x08
66 #define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dreg.h22 #define AR_CR 0x0008
23 #define AR_CR_RXE(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x0000000c : 0x00000004)
24 #define AR_CR_RXD 0x00000020
25 #define AR_CR_SWI 0x00000040
27 #define AR_RXDP 0x000C
29 #define AR_CFG 0x0014
30 #define AR_CFG_SWTD 0x00000001
31 #define AR_CFG_SWTB 0x00000002
32 #define AR_CFG_SWRD 0x00000004
33 #define AR_CFG_SWRB 0x00000008
[all …]
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gt_regs.h11 #define VLV_GUNIT_BASE 0x180000
25 #define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60)
26 #define MTL_CAGF_MASK REG_GENMASK(8, 0)
27 #define MTL_CC0 0x0
28 #define MTL_CC6 0x3
32 #define RPM_CONFIG0 _MMIO(0xd00)
35 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0
38 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SH…
39 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0
44 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_…
[all …]
/linux/drivers/net/ethernet/renesas/
H A Drswitch.h18 for (i = 0; i < RSWITCH_NUM_PORTS; i++) \
24 for (; i-- > 0; ) \
45 #define RSWITCH_TOP_OFFSET 0x00008000
46 #define RSWITCH_COMA_OFFSET 0x00009000
47 #define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */
48 #define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */
49 #define RSWITCH_GWCA0_OFFSET 0x00010000
50 #define RSWITCH_GWCA1_OFFSET 0x00012000
56 #define GWCA_INDEX 0
58 #define GWCA_IPV_NUM 0
[all …]
/linux/drivers/media/dvb-frontends/
H A Dds3000.c27 } while (0)
37 0x23, 0x05,
38 0x08, 0x03,
39 0x0c, 0x00,
40 0x21, 0x54,
41 0x25, 0x82,
42 0x27, 0x31,
43 0x30, 0x08,
44 0x31, 0x40,
45 0x32, 0x32,
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-apq8064.dtsi25 reg = <0x80000000 0x200000>;
30 reg = <0x8f000000 0x700000>;
37 #size-cells = <0>;
39 cpu0: cpu@0 {
43 reg = <0>;
100 memory@0 {
102 reg = <0x0 0x0>;
111 coefficients = <1199 0>;
132 coefficients = <1132 0>;
153 coefficients = <1199 0>;
[all …]
/linux/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c41 } while (0)
52 } while (0)
71 #define RING_REG(base) _MMIO((base) + 0x28) in iterate_generic_mmio()
75 #define RING_REG(base) _MMIO((base) + 0x134) in iterate_generic_mmio()
79 #define RING_REG(base) _MMIO((base) + 0x6c) in iterate_generic_mmio()
82 MMIO_D(_MMIO(0x2148)); in iterate_generic_mmio()
84 MMIO_D(_MMIO(0x12198)); in iterate_generic_mmio()
93 #define RING_REG(base) _MMIO((base) + 0x29c) in iterate_generic_mmio()
105 MMIO_D(_MMIO(0x2124)); in iterate_generic_mmio()
106 MMIO_D(_MMIO(0x20dc)); in iterate_generic_mmio()
[all …]
/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A Dother.json3 "EventCode": "0x3084",
8 "EventCode": "0xF880",
13 "EventCode": "0x4088",
18 "EventCode": "0x20A4",
23 "EventCode": "0x40008",
28 "EventCode": "0x20064",
33 "EventCode": "0x260B4",
38 "EventCode": "0x20006",
43 "EventCode": "0x201E4",
48 "EventCode": "0x4E044",
[all …]
/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra234.c1433 .mux_bit = 0, \
1447 #define drive_soc_gpio08_pb0 DRV_PINGROUP_ENTRY_Y(0x500c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1448 #define drive_soc_gpio36_pm5 DRV_PINGROUP_ENTRY_Y(0x10004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1449 #define drive_soc_gpio53_pm6 DRV_PINGROUP_ENTRY_Y(0x1000c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1450 #define drive_soc_gpio55_pm4 DRV_PINGROUP_ENTRY_Y(0x10014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1451 #define drive_soc_gpio38_pm7 DRV_PINGROUP_ENTRY_Y(0x1001c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1452 #define drive_soc_gpio39_pn1 DRV_PINGROUP_ENTRY_Y(0x10024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1453 #define drive_soc_gpio40_pn2 DRV_PINGROUP_ENTRY_Y(0x1002c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1454 #define drive_dp_aux_ch0_hpd_pm0 DRV_PINGROUP_ENTRY_Y(0x10034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1455 #define drive_dp_aux_ch1_hpd_pm1 DRV_PINGROUP_ENTRY_Y(0x1003c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
[all …]
H A Dpinctrl-tegra194.c1333 .mux_bit = 0, \
1348 …efine drive_soc_gpio33_pt0 DRV_PINGROUP_ENTRY_Y(0x1004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1349 …efine drive_soc_gpio32_ps7 DRV_PINGROUP_ENTRY_Y(0x100c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1350 …efine drive_soc_gpio31_ps6 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1351 …efine drive_soc_gpio30_ps5 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1352 …efine drive_aud_mclk_ps4 DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1353 …efine drive_dap1_fs_ps3 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1354 …efine drive_dap1_din_ps2 DRV_PINGROUP_ENTRY_Y(0x1034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1355 …efine drive_dap1_dout_ps1 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1356 …efine drive_dap1_sclk_ps0 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
[all …]
/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-reg.h13 #define AFE_SRAM_BASE (0x10880000)
14 #define AFE_SRAM_SIZE (0x10000)
16 #define AUDIO_TOP_CON0 (0x0000)
17 #define AUDIO_TOP_CON1 (0x0004)
18 #define AUDIO_TOP_CON2 (0x0008)
19 #define AUDIO_TOP_CON3 (0x000c)
20 #define AUDIO_TOP_CON4 (0x0010)
21 #define AUDIO_TOP_CON5 (0x0014)
22 #define AUDIO_TOP_CON6 (0x0018)
23 #define AFE_MAS_HADDR_MSB (0x0020)
[all …]
/linux/sound/soc/mediatek/mt8188/
H A Dmt8188-reg.h14 #define AUDIO_TOP_CON0 (0x0000)
15 #define AUDIO_TOP_CON1 (0x0004)
16 #define AUDIO_TOP_CON2 (0x0008)
17 #define AUDIO_TOP_CON3 (0x000c)
18 #define AUDIO_TOP_CON4 (0x0010)
19 #define AUDIO_TOP_CON5 (0x0014)
20 #define AUDIO_TOP_CON6 (0x0018)
21 #define AFE_MAS_HADDR_MSB (0x0020)
22 #define AFE_MEMIF_ONE_HEART (0x0024)
23 #define AFE_MUX_SEL_CFG (0x0044)
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h26 #define ixATTR00 0x0000
27 #define ixATTR01 0x0001
28 #define ixATTR02 0x0002
29 #define ixATTR03 0x0003
30 #define ixATTR04 0x0004
31 #define ixATTR05 0x0005
32 #define ixATTR06 0x0006
33 #define ixATTR07 0x0007
34 #define ixATTR08 0x0008
35 #define ixATTR09 0x0009
[all …]
H A Ddce_8_0_d.h27 #define mmPIPE0_PG_CONFIG 0x1760
28 #define mmPIPE0_PG_ENABLE 0x1761
29 #define mmPIPE0_PG_STATUS 0x1762
30 #define mmPIPE1_PG_CONFIG 0x1764
31 #define mmPIPE1_PG_ENABLE 0x1765
32 #define mmPIPE1_PG_STATUS 0x1766
33 #define mmPIPE2_PG_CONFIG 0x1768
34 #define mmPIPE2_PG_ENABLE 0x1769
35 #define mmPIPE2_PG_STATUS 0x176a
36 #define mmPIPE3_PG_CONFIG 0x176c
[all …]
H A Ddce_11_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmDCFEV0_PG_CONFIG 0x2db
[all …]
H A Ddce_10_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]
/linux/drivers/net/ethernet/sun/
H A Dcassini.h8 * vendor id: 0x108E (Sun Microsystems, Inc.)
9 * device id: 0xabba (Cassini)
10 * revision ids: 0x01 = Cassini
11 * 0x02 = Cassini rev 2
12 * 0x10 = Cassini+
13 * 0x11 = Cassini+ 0.2u
15 * vendor id: 0x100b (National Semiconductor)
16 * device id: 0x0035 (DP83065/Saturn)
17 * revision ids: 0x30 = Saturn B2
19 * rings are all offset from 0.
[all …]
/linux/tools/perf/pmu-events/arch/powerpc/power8/
H A Dother.json3 "EventCode": "0x1f05e",
9 "EventCode": "0x2006e",
11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to …
15 "EventCode": "0x4e05e",
17 …"BriefDescription": "Number of cycles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 bel…
21 "EventCode": "0x610050",
27 "EventCode": "0x520050",
33 "EventCode": "0x620052",
39 "EventCode": "0x610052",
45 "EventCode": "0x610054",
[all …]
/linux/drivers/gpu/drm/i915/gvt/
H A Dhandlers.c66 #define PCH_PP_STATUS _MMIO(0xc7200)
67 #define PCH_PP_CONTROL _MMIO(0xc7204)
68 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
69 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
70 #define PCH_PP_DIVISOR _MMIO(0xc7210)
87 return 0; in intel_gvt_get_device_type()
128 return 0; in setup_mmio_info()
150 return 0; in setup_mmio_info()
167 offset &= ~GENMASK(11, 0); in intel_gvt_render_mmio_to_engine()
176 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
[all …]

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