Lines Matching +full:0 +full:x4094
70 #define PCH_PP_STATUS _MMIO(0xc7200)
71 #define PCH_PP_CONTROL _MMIO(0xc7204)
72 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
73 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
74 #define PCH_PP_DIVISOR _MMIO(0xc7210)
91 return 0;
132 return 0;
154 return 0;
171 offset &= ~GENMASK(11, 0);
180 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
183 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
222 memset(p_data, 0, bytes);
225 return 0;
250 return 0;
263 return 0;
283 return 0;
288 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
313 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset);
321 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
322 return 0;
328 intel_engine_mask_t engine_mask = 0;
369 vgpu_vreg(vgpu, offset) = 0;
371 return 0;
401 return 0;
413 return 0;
431 return 0;
438 case 0xe651c:
439 case 0xe661c:
440 case 0xe671c:
441 case 0xe681c:
444 case 0xe6c04:
445 vgpu_vreg(vgpu, offset) = 0x3;
447 case 0xe6e1c:
448 vgpu_vreg(vgpu, offset) = 0x2f << 16;
455 return 0;
476 u32 dp_br = 0;
502 gvt_dbg_dpy("vgpu-%d PORT_%c can't get freq from SPLL 0x%08x\n",
527 gvt_dbg_dpy("vgpu-%d PORT_%c WRPLL can't get refclk 0x%08x\n",
540 gvt_dbg_dpy("vgpu-%d PORT_%c has invalid clock select 0x%08x\n",
551 u32 dp_br = 0;
579 gvt_dbg_dpy("vgpu-%d PORT_%c PLL_ENABLE 0x%08x isn't enabled or locked\n",
586 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0))) << 22;
599 if (clock.n == 0 || clock.p == 0) {
615 u32 dp_br = 0;
653 dp_br = 0;
693 u64 pixel_clk = 0;
694 u32 new_rate = 0;
702 new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal + 1, vtotal + 1));
728 return 0;
733 _MMIO(0xd80),
734 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)
735 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)
736 CL_PRIMITIVES_COUNT, //_MMIO(0x2340)
737 PS_INVOCATION_COUNT, //_MMIO(0x2348)
738 PS_DEPTH_COUNT, //_MMIO(0x2350)
739 GEN8_CS_CHICKEN1,//_MMIO(0x2580)
740 _MMIO(0x2690),
741 _MMIO(0x2694),
742 _MMIO(0x2698),
743 _MMIO(0x2754),
744 _MMIO(0x28a0),
745 _MMIO(0x4de0),
746 _MMIO(0x4de4),
747 _MMIO(0x4dfc),
748 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010)
749 _MMIO(0x7014),
750 HDC_CHICKEN0,//_MMIO(0x7300)
751 GEN8_HDC_CHICKEN1,//_MMIO(0x7304)
752 _MMIO(0x7700),
753 _MMIO(0x7704),
754 _MMIO(0x7708),
755 _MMIO(0x770c),
756 _MMIO(0x83a8),
757 _MMIO(0xb110),
758 _MMIO(0xb118),
759 _MMIO(0xe100),
760 _MMIO(0xe18c),
761 _MMIO(0xe48c),
762 _MMIO(0xe5f4),
763 _MMIO(0x64844),
769 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list);
805 return 0;
821 return 0;
828 return 0;
831 #define FDI_LINK_TRAIN_PATTERN1 0
847 return 0;
880 return 0;
888 return 0;
891 #define INVALID_INDEX (~0U)
939 if (ret < 0)
945 if (ret < 0)
954 return 0;
971 if (data == 0x2) {
975 return 0;
990 return 0;
1003 return 0;
1018 return 0;
1042 return 0;
1062 return 0;
1088 return 0;
1114 return 0;
1131 value &= ~(0xf << 20);
1137 return 0;
1176 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8)
1193 return 0;
1202 return 0;
1208 return 0;
1213 vgpu_vreg(vgpu, offset) = 0;
1214 return 0;
1222 addr = (msg >> 8) & 0xffff;
1223 ctrl = (msg >> 24) & 0xff;
1224 len = msg & 0xff;
1243 return 0;
1257 for (t = 0; t < 4; t++) {
1260 buf[t * 4] = (r >> 24) & 0xff;
1261 buf[t * 4 + 1] = (r >> 16) & 0xff;
1262 buf[t * 4 + 2] = (r >> 8) & 0xff;
1263 buf[t * 4 + 3] = r & 0xff;
1268 for (t = 0; t <= len; t++) {
1280 vgpu_vreg(vgpu, offset + 4) = 0;
1283 return 0;
1287 int idx, i, ret = 0;
1299 vgpu_vreg(vgpu, offset + 4) = 0;
1300 vgpu_vreg(vgpu, offset + 8) = 0;
1301 vgpu_vreg(vgpu, offset + 12) = 0;
1302 vgpu_vreg(vgpu, offset + 16) = 0;
1303 vgpu_vreg(vgpu, offset + 20) = 0;
1307 return 0;
1312 vgpu_vreg(vgpu, offset + 4 * idx) = 0;
1336 ret = 0;
1342 return 0;
1350 return 0;
1358 return 0;
1371 return 0;
1381 for (i = 0; i < num; ++i)
1386 return 0;
1398 for (i = 0; i < num; ++i) {
1426 return 0;
1452 return 0;
1476 case 0x78010: /* vgt_caps */
1477 case 0x7881c:
1487 return 0;
1496 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));
1515 return 0;
1526 env[0] = display_ready_str;
1542 send_display_ready_uevent(vgpu, data ? 1 : 0);
1550 case _vgtif_reg(pdp[0].lo):
1551 case _vgtif_reg(pdp[0].hi):
1561 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
1575 return 0;
1590 return 0;
1608 return 0;
1621 return 0;
1631 return 0;
1647 return 0;
1650 return 0;
1659 if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
1667 return 0;
1674 return 0;
1680 u32 v = 0;
1682 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))
1683 v |= (1 << 0);
1685 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))
1688 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))
1691 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))
1703 u32 cmd = value & 0xff;
1718 *data0 = 0x1e1a1100;
1720 *data0 = 0x61514b3d;
1728 *data0 = 0x16080707;
1730 *data0 = 0x16161616;
1741 *data0 |= 0x1;
1764 if (value != 0 &&
1766 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n",
1777 gvt_vgpu_err("access unknown hardware status page register:0x%x\n",
1782 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n",
1814 return 0;
1827 return 0;
1840 return 0;
1847 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0;
1861 return 0;
1882 vgpu_vreg(vgpu, offset - 0x600) = v;
1883 vgpu_vreg(vgpu, offset - 0x800) = v;
1885 vgpu_vreg(vgpu, offset - 0x400) = v;
1886 vgpu_vreg(vgpu, offset - 0x600) = v;
1891 return 0;
1899 if (v & BIT(0)) {
1916 return 0;
1922 vgpu_vreg(vgpu, offset) = 0;
1923 return 0;
1933 * PML4 PTE: PAT(0) PCD(1) PWT(1).
1940 GEN8_PPAT(0, CHV_PPAT_SNOOP) |
1941 GEN8_PPAT(1, 0) |
1942 GEN8_PPAT(2, 0) |
1951 return 0;
1961 return 0;
2000 int ret = 0;
2031 execlist->elsp_dwords.index &= 0x3;
2052 return 0;
2059 return 0;
2070 return 0;
2081 return 0;
2091 return 0;
2097 unsigned int id = 0;
2100 vgpu_vreg(vgpu, offset) = 0;
2103 case 0x4260:
2106 case 0x4264:
2109 case 0x4268:
2112 case 0x426c:
2115 case 0x4270:
2123 return 0;
2140 return 0;
2149 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18);
2152 if (IS_MASKED_BITS_ENABLED(data, 0x10) ||
2153 IS_MASKED_BITS_ENABLED(data, 0x8))
2156 return 0;
2164 } while (0)
2167 MMIO_F(reg, 4, 0, 0, 0, d, r, w)
2170 MMIO_F(reg, 4, f, 0, 0, d, r, w)
2173 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
2176 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
2179 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
2188 } while (0)
2191 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
2194 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
2197 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
2200 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
2208 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
2211 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
2212 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
2213 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
2215 MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
2225 #define RING_REG(base) _MMIO((base) + 0x28)
2229 #define RING_REG(base) _MMIO((base) + 0x134)
2233 #define RING_REG(base) _MMIO((base) + 0x6c)
2234 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
2238 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
2240 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
2242 MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
2243 MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
2244 MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
2245 MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
2249 #define RING_REG(base) _MMIO((base) + 0x29c)
2269 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2271 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2273 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2276 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2282 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
2283 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
2284 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
2285 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
2286 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
2287 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
2288 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2289 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2321 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
2323 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
2325 MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2327 MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2329 MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2347 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
2348 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
2349 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
2350 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
2351 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
2352 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
2354 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
2367 MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4, 0, 0, 0, D_ALL, NULL,
2408 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
2418 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2419 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2420 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2421 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2422 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2424 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
2425 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2426 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2427 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2429 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2430 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2433 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2434 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2435 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2436 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2437 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2438 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2439 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2440 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2441 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2442 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2443 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2444 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2445 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2446 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2447 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2448 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2449 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2453 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2454 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2455 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2458 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2459 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2460 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2461 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2467 return 0;
2474 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2475 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2476 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2526 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
2529 #define RING_REG(base) _MMIO((base) + 0xd0)
2530 MMIO_RING_F(RING_REG, 4, F_RO, 0,
2535 #define RING_REG(base) _MMIO((base) + 0x230)
2536 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
2539 #define RING_REG(base) _MMIO((base) + 0x234)
2540 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
2544 #define RING_REG(base) _MMIO((base) + 0x244)
2548 #define RING_REG(base) _MMIO((base) + 0x370)
2549 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
2552 #define RING_REG(base) _MMIO((base) + 0x3a0)
2558 #define RING_REG(base) _MMIO((base) + 0x270)
2559 MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
2572 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2573 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2575 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
2576 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
2578 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
2581 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
2583 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
2585 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2586 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2588 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2590 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
2592 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2593 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2594 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2595 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2596 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2597 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2598 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2599 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2600 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2601 MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2602 return 0;
2616 MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2618 MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2620 MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2625 MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
2634 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2636 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2638 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2641 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2643 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2645 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2648 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2650 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2652 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2655 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2660 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2665 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2674 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2678 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2682 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2690 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2695 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2700 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2705 MMIO_DH(PLANE_AUX_DIST(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2710 MMIO_DH(PLANE_AUX_DIST(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2715 MMIO_DH(PLANE_AUX_DIST(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2720 MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2725 MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2730 MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2737 MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
2739 MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
2748 MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2755 MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
2761 #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
2771 MMIO_DFH(_MMIO(0xe4cc), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2773 return 0;
2794 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT,
2798 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT,
2802 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT,
2807 MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
2808 MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
2809 0, 0, D_BXT, NULL, NULL);
2810 MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
2811 0, 0, D_BXT, NULL, NULL);
2812 MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
2813 0, 0, D_BXT, NULL, NULL);
2814 MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
2815 0, 0, D_BXT, NULL, NULL);
2821 return 0;
2831 for (i = 0; i < num; i++, block++) {
2858 gvt->mmio.num_mmio_block = 0;
2900 return 0;
2920 memset(block, 0, sizeof(*block));
2927 return 0;
2933 if (size < 1024 || offset == i915_mmio_reg_offset(GEN9_GFX_MOCS(0)))
2964 return 0;
3026 return 0;
3055 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) {
3060 for (j = 0; j < block->size; j += 4) {
3066 return 0;
3083 return 0;
3100 return 0;
3124 return 0;
3175 u32 old_vreg = 0;
3176 u64 data = 0;
3186 return 0;
3221 for (i = 0; i < vgpu_fence_sz(vgpu); i++)
3235 return 0;