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/linux/drivers/gpu/host1x/hw/
H A Dhw_host1x08_common.h6 #define HOST1X_COMMON_OFA_MLOCK 0x4050
7 #define HOST1X_COMMON_NVJPG1_MLOCK 0x4070
8 #define HOST1X_COMMON_VIC_MLOCK 0x4078
9 #define HOST1X_COMMON_NVENC_MLOCK 0x407c
10 #define HOST1X_COMMON_NVDEC_MLOCK 0x4080
11 #define HOST1X_COMMON_NVJPG_MLOCK 0x4084
/linux/drivers/gpu/drm/amd/amdgpu/
H A Djpeg_v4_0_3.h27 #define regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 0x1bfff
28 #define regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x404d
29 #define regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x404e
30 #define regUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x404f
31 #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ab
32 #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40ac
33 #define regUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40a4
34 #define regUVD_LMI_JPEG_VMID_INTERNAL_OFFSET 0x40a6
35 #define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40b6
36 #define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40b7
[all …]
H A Djpeg_v2_0.h27 #define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 0x1bfff
28 #define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x4029
29 #define mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x402a
30 #define mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x402b
31 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ea
32 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40eb
33 #define mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40cf
34 #define mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET 0x40d1
35 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40e8
36 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40e9
[all …]
/linux/Documentation/devicetree/bindings/soc/ti/
H A Dti,j721e-system-controller.yaml48 "^mux-controller@[0-9a-f]+$":
53 "^clock-controller@[0-9a-f]+$":
59 "phy@[0-9a-f]+$":
65 "^chipid@[0-9a-f]+$":
84 reg = <0x00100000 0x1c000>;
91 reg = <0x00004080 0x50>;
95 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
96 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
97 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
98 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
[all …]
/linux/drivers/dma/xilinx/
H A Dxdma-regs.h32 #define XDMA_DESC_MAGIC 0xad4bUL
34 #define XDMA_DESC_FLAGS_BITS GENMASK(7, 0)
35 #define XDMA_DESC_STOPPED BIT(0)
75 #define XDMA_CHAN_IDENTIFIER 0x0
76 #define XDMA_CHAN_CONTROL 0x4
77 #define XDMA_CHAN_CONTROL_W1S 0x8
78 #define XDMA_CHAN_CONTROL_W1C 0xc
79 #define XDMA_CHAN_STATUS 0x40
80 #define XDMA_CHAN_STATUS_RC 0x44
81 #define XDMA_CHAN_COMPLETED_DESC 0x48
[all …]
/linux/lib/
H A Dcrc-itu-t.c10 /* CRC table for the CRC ITU-T V.41 0x1021 (x^16 + x^12 + x^5 + 1) */
12 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7,
13 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef,
14 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6,
15 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de,
16 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485,
17 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d,
18 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4,
19 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc,
20 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823,
[all …]
/linux/drivers/net/ethernet/tehuti/
H A Dtn40_regs.h8 #define TN40_REGS_SIZE 0x10000
10 /* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */
11 #define TN40_REG_TXD_CFG1_0 0x4000
12 #define TN40_REG_TXD_CFG1_1 0x4004
13 #define TN40_REG_TXD_CFG1_2 0x4008
14 #define TN40_REG_TXD_CFG1_3 0x400C
16 #define TN40_REG_RXF_CFG1_0 0x4010
17 #define TN40_REG_RXF_CFG1_1 0x4014
18 #define TN40_REG_RXF_CFG1_2 0x4018
19 #define TN40_REG_RXF_CFG1_3 0x401C
[all …]
/linux/drivers/gpu/drm/radeon/reg_srcs/
H A Drv5151 rv515 0x6d40
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dt4_pci_id_tbl.h46 * -- The PCI Function Number to use in the PCI Device ID Table. "0"
73 /* T4 and later ASICs use a PCI Device ID scheme of 0xVFPP where:
76 * F = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs
97 CH_PCI_ID_TABLE_FENTRY(0x4000), /* T440-dbg */
98 CH_PCI_ID_TABLE_FENTRY(0x4001), /* T420-cr */
99 CH_PCI_ID_TABLE_FENTRY(0x4002), /* T422-cr */
100 CH_PCI_ID_TABLE_FENTRY(0x4003), /* T440-cr */
101 CH_PCI_ID_TABLE_FENTRY(0x4004), /* T420-bch */
102 CH_PCI_ID_TABLE_FENTRY(0x4005), /* T440-bch */
103 CH_PCI_ID_TABLE_FENTRY(0x4006), /* T440-ch */
[all …]
/linux/include/linux/mfd/wm831x/
H A Dcore.h25 #define WM831X_RESET_ID 0x00
26 #define WM831X_REVISION 0x01
27 #define WM831X_PARENT_ID 0x4000
28 #define WM831X_SYSVDD_CONTROL 0x4001
29 #define WM831X_THERMAL_MONITORING 0x4002
30 #define WM831X_POWER_STATE 0x4003
31 #define WM831X_WATCHDOG 0x4004
32 #define WM831X_ON_PIN_CONTROL 0x4005
33 #define WM831X_RESET_CONTROL 0x4006
34 #define WM831X_CONTROL_INTERFACE 0x4007
[all …]
H A Dregulator.h14 * R16462 (0x404E) - Current Sink 1
16 #define WM831X_CS1_ENA 0x8000 /* CS1_ENA */
17 #define WM831X_CS1_ENA_MASK 0x8000 /* CS1_ENA */
20 #define WM831X_CS1_DRIVE 0x4000 /* CS1_DRIVE */
21 #define WM831X_CS1_DRIVE_MASK 0x4000 /* CS1_DRIVE */
24 #define WM831X_CS1_SLPENA 0x1000 /* CS1_SLPENA */
25 #define WM831X_CS1_SLPENA_MASK 0x1000 /* CS1_SLPENA */
28 #define WM831X_CS1_OFF_RAMP_MASK 0x0C00 /* CS1_OFF_RAMP - [11:10] */
31 #define WM831X_CS1_ON_RAMP_MASK 0x0300 /* CS1_ON_RAMP - [9:8] */
34 #define WM831X_CS1_ISEL_MASK 0x003F /* CS1_ISEL - [5:0] */
[all …]
/linux/drivers/net/wireless/mediatek/mt7601u/
H A Dregs.h12 #define MT_ASIC_VERSION 0x0000
14 #define MT76XX_REV_E3 0x22
15 #define MT76XX_REV_E4 0x33
17 #define MT_CMB_CTRL 0x0020
21 #define MT_EFUSE_CTRL 0x0024
22 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
30 #define MT_EFUSE_DATA_BASE 0x0028
33 #define MT_COEXCFG0 0x0040
34 #define MT_COEXCFG0_COEX_EN BIT(0)
36 #define MT_WLAN_FUN_CTRL 0x0080
[all …]
/linux/drivers/net/ethernet/agere/
H A Det131x.h53 #define LBCIF_DWORD0_GROUP 0xAC
54 #define LBCIF_DWORD1_GROUP 0xB0
57 #define LBCIF_ADDRESS_REGISTER 0xAC
58 #define LBCIF_DATA_REGISTER 0xB0
59 #define LBCIF_CONTROL_REGISTER 0xB1
60 #define LBCIF_STATUS_REGISTER 0xB2
63 #define LBCIF_CONTROL_SEQUENTIAL_READ 0x01
64 #define LBCIF_CONTROL_PAGE_WRITE 0x02
65 #define LBCIF_CONTROL_EEPROM_RELOAD 0x08
66 #define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20
[all …]
/linux/drivers/video/fbdev/
H A Dgxt4500.c19 #define PCI_DEVICE_ID_IBM_GXT4500P 0x21c
20 #define PCI_DEVICE_ID_IBM_GXT6500P 0x21b
21 #define PCI_DEVICE_ID_IBM_GXT4000P 0x16e
22 #define PCI_DEVICE_ID_IBM_GXT6000P 0x170
27 #define CFG_ENDIAN0 0x40
30 #define STATUS 0x1000
31 #define CTRL_REG0 0x1004
32 #define CR0_HALT_DMA 0x4
33 #define CR0_RASTER_RESET 0x8
34 #define CR0_GEOM_RESET 0x10
[all …]
/linux/drivers/clk/qcom/
H A Dmmcc-apq8084.c44 .l_reg = 0x0004,
45 .m_reg = 0x0008,
46 .n_reg = 0x000c,
47 .config_reg = 0x0014,
48 .mode_reg = 0x0000,
49 .status_reg = 0x001c,
62 .enable_reg = 0x0100,
63 .enable_mask = BIT(0),
75 .l_reg = 0x0044,
76 .m_reg = 0x0048,
[all …]
H A Dcamcc-sc7180.c35 { 600000000, 3300000000UL, 0 },
39 { 249600000, 2000000000UL, 0 },
44 .l = 0x1f,
45 .alpha = 0x4000,
46 .config_ctl_val = 0x20485699,
47 .config_ctl_hi_val = 0x00002067,
48 .test_ctl_val = 0x40000000,
49 .user_ctl_hi_val = 0x00004805,
50 .user_ctl_val = 0x00000001,
54 .offset = 0x0,
[all …]
H A Dmmcc-msm8996.c64 { 1500000000, 2000000000, 0 },
70 { 1500000000, 2000000000, 0 },
74 { 500000000, 1500000000, 0 },
78 .offset = 0x0,
83 .enable_reg = 0x100,
84 .enable_mask = BIT(0),
97 .offset = 0x0,
112 .offset = 0x30,
117 .enable_reg = 0x100,
131 .offset = 0x30,
[all …]
H A Dcamcc-sm6350.c36 { 249600000, 2000000000, 0 },
41 .l = 0x1f,
42 .alpha = 0x4000,
43 .config_ctl_val = 0x20485699,
44 .config_ctl_hi_val = 0x00002067,
45 .test_ctl_val = 0x40000000,
46 .test_ctl_hi_val = 0x00000002,
47 .user_ctl_val = 0x00000101,
48 .user_ctl_hi_val = 0x00004805,
52 .offset = 0x0,
[all …]
/linux/drivers/net/wireless/microchip/wilc1000/
H A Dwlan_if.h22 WILC_FW_BSS_TYPE_INFRA = 0,
28 WILC_FW_OPER_MODE_B_ONLY = 0, /* 1, 2 M, otherwise 5, 11 M */
35 WILC_FW_PREAMBLE_SHORT = 0, /* Short Preamble */
41 WILC_FW_PASSIVE_SCAN = 0,
46 WILC_FW_NO_POWERSAVE = 0,
54 WILC_BUS_ACQUIRE_ONLY = 0,
59 WILC_BUS_RELEASE_ONLY = 0,
64 WILC_FW_NO_ENCRYPT = 0,
65 WILC_FW_ENCRYPT_ENABLED = BIT(0),
97 WILC_FW_MFP_NONE = 0x0,
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dreg.h22 #define AR_CR 0x0008
23 #define AR_CR_RXE(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x0000000c : 0x00000004)
24 #define AR_CR_RXD 0x00000020
25 #define AR_CR_SWI 0x00000040
27 #define AR_RXDP 0x000C
29 #define AR_CFG 0x0014
30 #define AR_CFG_SWTD 0x00000001
31 #define AR_CFG_SWTB 0x00000002
32 #define AR_CFG_SWRD 0x00000004
33 #define AR_CFG_SWRB 0x00000008
[all …]
/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A Dother.json3 "EventCode": "0x3084",
8 "EventCode": "0xF880",
13 "EventCode": "0x4088",
18 "EventCode": "0x20A4",
23 "EventCode": "0x40008",
28 "EventCode": "0x20064",
33 "EventCode": "0x260B4",
38 "EventCode": "0x20006",
43 "EventCode": "0x201E4",
48 "EventCode": "0x4E044",
[all …]
/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra234.c1433 .mux_bit = 0, \
1447 #define drive_soc_gpio08_pb0 DRV_PINGROUP_ENTRY_Y(0x500c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1448 #define drive_soc_gpio36_pm5 DRV_PINGROUP_ENTRY_Y(0x10004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1449 #define drive_soc_gpio53_pm6 DRV_PINGROUP_ENTRY_Y(0x1000c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1450 #define drive_soc_gpio55_pm4 DRV_PINGROUP_ENTRY_Y(0x10014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1451 #define drive_soc_gpio38_pm7 DRV_PINGROUP_ENTRY_Y(0x1001c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1452 #define drive_soc_gpio39_pn1 DRV_PINGROUP_ENTRY_Y(0x10024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1453 #define drive_soc_gpio40_pn2 DRV_PINGROUP_ENTRY_Y(0x1002c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1454 #define drive_dp_aux_ch0_hpd_pm0 DRV_PINGROUP_ENTRY_Y(0x10034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1455 #define drive_dp_aux_ch1_hpd_pm1 DRV_PINGROUP_ENTRY_Y(0x1003c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
[all …]
/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-reg.h13 #define AFE_SRAM_BASE (0x10880000)
14 #define AFE_SRAM_SIZE (0x10000)
16 #define AUDIO_TOP_CON0 (0x0000)
17 #define AUDIO_TOP_CON1 (0x0004)
18 #define AUDIO_TOP_CON2 (0x0008)
19 #define AUDIO_TOP_CON3 (0x000c)
20 #define AUDIO_TOP_CON4 (0x0010)
21 #define AUDIO_TOP_CON5 (0x0014)
22 #define AUDIO_TOP_CON6 (0x0018)
23 #define AFE_MAS_HADDR_MSB (0x0020)
[all …]
/linux/drivers/net/wireless/ath/ath5k/
H A Dreg.h46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
52 #define AR5K_CR 0x0008 /* Register Address */
53 #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */
54 #define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */
55 #define AR5K_CR_RXE 0x00000004 /* RX Enable */
56 #define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */
57 #define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */
58 #define AR5K_CR_RXD 0x00000020 /* RX Disable */
59 #define AR5K_CR_SWI 0x00000040 /* Software Interrupt */
[all …]
/linux/sound/soc/mediatek/mt8188/
H A Dmt8188-reg.h14 #define AUDIO_TOP_CON0 (0x0000)
15 #define AUDIO_TOP_CON1 (0x0004)
16 #define AUDIO_TOP_CON2 (0x0008)
17 #define AUDIO_TOP_CON3 (0x000c)
18 #define AUDIO_TOP_CON4 (0x0010)
19 #define AUDIO_TOP_CON5 (0x0014)
20 #define AUDIO_TOP_CON6 (0x0018)
21 #define AFE_MAS_HADDR_MSB (0x0020)
22 #define AFE_MEMIF_ONE_HEART (0x0024)
23 #define AFE_MUX_SEL_CFG (0x0044)
[all …]

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