Lines Matching +full:0 +full:x4084
62 { 1500000000, 2000000000, 0 },
68 { 1500000000, 2000000000, 0 },
72 { 500000000, 1500000000, 0 },
76 .offset = 0x0,
81 .enable_reg = 0x100,
82 .enable_mask = BIT(0),
95 .offset = 0x0,
110 .offset = 0x30,
115 .enable_reg = 0x100,
129 .offset = 0x30,
144 .offset = 0x4100,
159 .offset = 0x4100,
174 .offset = 0x60,
189 .offset = 0x60,
204 .offset = 0x90,
219 .offset = 0x90,
234 .offset = 0xc0,
249 .offset = 0xc0,
264 .offset = 0x4130,
279 .offset = 0x4130,
294 .offset = 0x4200,
309 .offset = 0x4200,
324 { P_XO, 0 },
334 { P_XO, 0 },
346 { P_XO, 0 },
358 { P_XO, 0 },
370 { P_XO, 0 },
384 { P_XO, 0 },
400 { P_XO, 0 },
416 { P_XO, 0 },
432 { P_XO, 0 },
448 { P_XO, 0 },
466 { P_XO, 0 },
486 { P_XO, 0 },
506 F(19200000, P_XO, 1, 0, 0),
507 F(40000000, P_GPLL0_DIV, 7.5, 0, 0),
508 F(80000000, P_MMPLL0, 10, 0, 0),
513 .cmd_rcgr = 0x5000,
526 F(19200000, P_XO, 1, 0, 0),
527 F(75000000, P_GPLL0_DIV, 4, 0, 0),
528 F(100000000, P_GPLL0, 6, 0, 0),
529 F(171430000, P_GPLL0, 3.5, 0, 0),
530 F(200000000, P_GPLL0, 3, 0, 0),
531 F(320000000, P_MMPLL0, 2.5, 0, 0),
532 F(400000000, P_MMPLL0, 2, 0, 0),
537 .cmd_rcgr = 0x5040,
550 .cmd_rcgr = 0x5090,
564 .cmd_rcgr = 0x4000,
583 F(19200000, P_XO, 1, 0, 0),
588 .cmd_rcgr = 0x4090,
601 .cmd_rcgr = 0x4010,
613 F(19200000, P_XO, 1, 0, 0),
614 F(50000000, P_GPLL0, 12, 0, 0),
619 .cmd_rcgr = 0x4060,
632 F(75000000, P_GPLL0_DIV, 4, 0, 0),
633 F(150000000, P_GPLL0, 4, 0, 0),
634 F(346666667, P_MMPLL3, 3, 0, 0),
635 F(520000000, P_MMPLL3, 2, 0, 0),
640 .cmd_rcgr = 0x1000,
654 .cmd_rcgr = 0x1060,
668 .cmd_rcgr = 0x1080,
682 .cmd_rcgr = 0x2000,
696 .cmd_rcgr = 0x2020,
710 F(85714286, P_GPLL0, 7, 0, 0),
711 F(100000000, P_GPLL0, 6, 0, 0),
712 F(150000000, P_GPLL0, 4, 0, 0),
713 F(171428571, P_GPLL0, 3.5, 0, 0),
714 F(200000000, P_GPLL0, 3, 0, 0),
715 F(275000000, P_MMPLL5, 3, 0, 0),
716 F(300000000, P_GPLL0, 2, 0, 0),
717 F(330000000, P_MMPLL5, 2.5, 0, 0),
718 F(412500000, P_MMPLL5, 2, 0, 0),
723 .cmd_rcgr = 0x2040,
741 .cmd_rcgr = 0x2060,
755 F(19200000, P_XO, 1, 0, 0),
760 .cmd_rcgr = 0x2080,
773 F(19200000, P_XO, 1, 0, 0),
778 .cmd_rcgr = 0x2100,
791 .cmd_rcgr = 0x2120,
804 .cmd_rcgr = 0x2140,
817 F(19200000, P_XO, 1, 0, 0),
822 .cmd_rcgr = 0x2160,
835 .cmd_rcgr = 0x2180,
858 .cmd_rcgr = 0x3420,
872 .cmd_rcgr = 0x3450,
886 F(4800000, P_XO, 4, 0, 0),
889 F(9600000, P_XO, 2, 0, 0),
891 F(19200000, P_XO, 1, 0, 0),
900 .cmd_rcgr = 0x3360,
914 .cmd_rcgr = 0x3390,
928 .cmd_rcgr = 0x33c0,
942 .cmd_rcgr = 0x33f0,
956 F(19200000, P_XO, 1, 0, 0),
957 F(37500000, P_GPLL0, 16, 0, 0),
958 F(50000000, P_GPLL0, 12, 0, 0),
959 F(100000000, P_GPLL0, 6, 0, 0),
964 .cmd_rcgr = 0x3300,
978 F(100000000, P_GPLL0_DIV, 3, 0, 0),
979 F(200000000, P_GPLL0, 3, 0, 0),
980 F(266666667, P_MMPLL0, 3, 0, 0),
985 .cmd_rcgr = 0x3000,
998 .cmd_rcgr = 0x3030,
1011 .cmd_rcgr = 0x3060,
1024 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1025 F(200000000, P_GPLL0, 3, 0, 0),
1026 F(320000000, P_MMPLL4, 3, 0, 0),
1027 F(384000000, P_MMPLL4, 2.5, 0, 0),
1032 .cmd_rcgr = 0x3240,
1045 .cmd_rcgr = 0x3260,
1058 .cmd_rcgr = 0x3280,
1071 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1072 F(150000000, P_GPLL0, 4, 0, 0),
1073 F(228571429, P_MMPLL0, 3.5, 0, 0),
1074 F(266666667, P_MMPLL0, 3, 0, 0),
1075 F(320000000, P_MMPLL0, 2.5, 0, 0),
1076 F(480000000, P_MMPLL4, 2, 0, 0),
1081 .cmd_rcgr = 0x3500,
1094 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1095 F(150000000, P_GPLL0, 4, 0, 0),
1096 F(228571429, P_MMPLL0, 3.5, 0, 0),
1097 F(266666667, P_MMPLL0, 3, 0, 0),
1098 F(320000000, P_MMPLL0, 2.5, 0, 0),
1103 .cmd_rcgr = 0x3540,
1116 .cmd_rcgr = 0x3560,
1129 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1130 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1131 F(300000000, P_GPLL0, 2, 0, 0),
1132 F(320000000, P_MMPLL0, 2.5, 0, 0),
1133 F(480000000, P_MMPLL4, 2, 0, 0),
1134 F(600000000, P_GPLL0, 1, 0, 0),
1139 .cmd_rcgr = 0x3600,
1152 .cmd_rcgr = 0x3620,
1165 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1166 F(200000000, P_GPLL0, 3, 0, 0),
1167 F(320000000, P_MMPLL0, 2.5, 0, 0),
1168 F(480000000, P_MMPLL4, 2, 0, 0),
1169 F(640000000, P_MMPLL4, 1.5, 0, 0),
1174 .cmd_rcgr = 0x3640,
1187 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1188 F(200000000, P_GPLL0, 3, 0, 0),
1189 F(266666667, P_MMPLL0, 3, 0, 0),
1190 F(480000000, P_MMPLL4, 2, 0, 0),
1191 F(600000000, P_GPLL0, 1, 0, 0),
1196 .cmd_rcgr = 0x3090,
1209 .cmd_rcgr = 0x3100,
1222 .cmd_rcgr = 0x3160,
1235 .cmd_rcgr = 0x31c0,
1248 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1249 F(200000000, P_GPLL0, 3, 0, 0),
1250 F(400000000, P_MMPLL0, 2, 0, 0),
1255 .cmd_rcgr = 0x3b00,
1268 .halt_reg = 0x5024,
1270 .enable_reg = 0x5024,
1271 .enable_mask = BIT(0),
1285 .halt_reg = 0x5054,
1287 .enable_reg = 0x5054,
1288 .enable_mask = BIT(0),
1302 .halt_reg = 0x5018,
1304 .enable_reg = 0x5018,
1305 .enable_mask = BIT(0),
1319 .halt_reg = 0x5014,
1321 .enable_reg = 0x5014,
1322 .enable_mask = BIT(0),
1335 .halt_reg = 0x5074,
1337 .enable_reg = 0x5074,
1338 .enable_mask = BIT(0),
1352 .halt_reg = 0x3c44,
1354 .enable_reg = 0x3c44,
1355 .enable_mask = BIT(0),
1369 .halt_reg = 0x3c48,
1371 .enable_reg = 0x3c48,
1372 .enable_mask = BIT(0),
1386 .halt_reg = 0x3c04,
1388 .enable_reg = 0x3c04,
1389 .enable_mask = BIT(0),
1403 .halt_reg = 0x3c08,
1405 .enable_reg = 0x3c08,
1406 .enable_mask = BIT(0),
1420 .halt_reg = 0x3c14,
1422 .enable_reg = 0x3c14,
1423 .enable_mask = BIT(0),
1437 .halt_reg = 0x3c18,
1439 .enable_reg = 0x3c18,
1440 .enable_mask = BIT(0),
1454 .halt_reg = 0x3c24,
1456 .enable_reg = 0x3c24,
1457 .enable_mask = BIT(0),
1471 .halt_reg = 0x3c28,
1473 .enable_reg = 0x3c28,
1474 .enable_mask = BIT(0),
1488 .halt_reg = 0x2474,
1490 .enable_reg = 0x2474,
1491 .enable_mask = BIT(0),
1505 .halt_reg = 0x2478,
1507 .enable_reg = 0x2478,
1508 .enable_mask = BIT(0),
1522 .halt_reg = 0x2444,
1524 .enable_reg = 0x2444,
1525 .enable_mask = BIT(0),
1539 .halt_reg = 0x2448,
1541 .enable_reg = 0x2448,
1542 .enable_mask = BIT(0),
1556 .halt_reg = 0x2454,
1558 .enable_reg = 0x2454,
1559 .enable_mask = BIT(0),
1573 .halt_reg = 0x2458,
1575 .enable_reg = 0x2458,
1576 .enable_mask = BIT(0),
1590 .halt_reg = 0x1194,
1592 .enable_reg = 0x1194,
1593 .enable_mask = BIT(0),
1607 .halt_reg = 0x1198,
1609 .enable_reg = 0x1198,
1610 .enable_mask = BIT(0),
1624 .halt_reg = 0x1174,
1626 .enable_reg = 0x1174,
1627 .enable_mask = BIT(0),
1641 .halt_reg = 0x1178,
1643 .enable_reg = 0x1178,
1644 .enable_mask = BIT(0),
1658 .halt_reg = 0x5298,
1660 .enable_reg = 0x5298,
1661 .enable_mask = BIT(0),
1675 .halt_reg = 0x4028,
1677 .enable_reg = 0x4028,
1678 .enable_mask = BIT(0),
1692 .halt_reg = 0x40b0,
1694 .enable_reg = 0x40b0,
1695 .enable_mask = BIT(0),
1709 .halt_reg = 0x403c,
1711 .enable_reg = 0x403c,
1712 .enable_mask = BIT(0),
1726 .halt_reg = 0x4044,
1728 .enable_reg = 0x4044,
1729 .enable_mask = BIT(0),
1743 .halt_reg = 0x1204,
1745 .enable_reg = 0x1204,
1746 .enable_mask = BIT(0),
1760 .halt_reg = 0x1208,
1762 .enable_reg = 0x1208,
1763 .enable_mask = BIT(0),
1777 .halt_reg = 0x4084,
1779 .enable_reg = 0x4084,
1780 .enable_mask = BIT(0),
1794 .halt_reg = 0x4088,
1796 .enable_reg = 0x4088,
1797 .enable_mask = BIT(0),
1811 .halt_reg = 0x1028,
1813 .enable_reg = 0x1028,
1814 .enable_mask = BIT(0),
1828 .halt_reg = 0x1034,
1830 .enable_reg = 0x1034,
1831 .enable_mask = BIT(0),
1845 .halt_reg = 0x1038,
1847 .enable_reg = 0x1038,
1848 .enable_mask = BIT(0),
1862 .halt_reg = 0x1030,
1864 .enable_reg = 0x1030,
1865 .enable_mask = BIT(0),
1879 .halt_reg = 0x1048,
1881 .enable_reg = 0x1048,
1882 .enable_mask = BIT(0),
1896 .halt_reg = 0x104c,
1898 .enable_reg = 0x104c,
1899 .enable_mask = BIT(0),
1913 .halt_reg = 0x2308,
1915 .enable_reg = 0x2308,
1916 .enable_mask = BIT(0),
1930 .halt_reg = 0x230c,
1932 .enable_reg = 0x230c,
1933 .enable_mask = BIT(0),
1947 .halt_reg = 0x2310,
1949 .enable_reg = 0x2310,
1950 .enable_mask = BIT(0),
1964 .halt_reg = 0x2314,
1966 .enable_reg = 0x2314,
1967 .enable_mask = BIT(0),
1981 .halt_reg = 0x2318,
1983 .enable_reg = 0x2318,
1984 .enable_mask = BIT(0),
1998 .halt_reg = 0x231c,
2000 .enable_reg = 0x231c,
2001 .enable_mask = BIT(0),
2015 .halt_reg = 0x2324,
2017 .enable_reg = 0x2324,
2018 .enable_mask = BIT(0),
2032 .halt_reg = 0x2328,
2034 .enable_reg = 0x2328,
2035 .enable_mask = BIT(0),
2049 .halt_reg = 0x2338,
2051 .enable_reg = 0x2338,
2052 .enable_mask = BIT(0),
2066 .halt_reg = 0x233c,
2068 .enable_reg = 0x233c,
2069 .enable_mask = BIT(0),
2083 .halt_reg = 0x2340,
2085 .enable_reg = 0x2340,
2086 .enable_mask = BIT(0),
2100 .halt_reg = 0x2344,
2102 .enable_reg = 0x2344,
2103 .enable_mask = BIT(0),
2117 .halt_reg = 0x2348,
2119 .enable_reg = 0x2348,
2120 .enable_mask = BIT(0),
2134 .halt_reg = 0x3484,
2136 .enable_reg = 0x3484,
2137 .enable_mask = BIT(0),
2151 .halt_reg = 0x348c,
2153 .enable_reg = 0x348c,
2154 .enable_mask = BIT(0),
2168 .halt_reg = 0x3494,
2170 .enable_reg = 0x3494,
2171 .enable_mask = BIT(0),
2185 .halt_reg = 0x3444,
2187 .enable_reg = 0x3444,
2188 .enable_mask = BIT(0),
2202 .halt_reg = 0x3474,
2204 .enable_reg = 0x3474,
2205 .enable_mask = BIT(0),
2219 .halt_reg = 0x3384,
2221 .enable_reg = 0x3384,
2222 .enable_mask = BIT(0),
2236 .halt_reg = 0x33b4,
2238 .enable_reg = 0x33b4,
2239 .enable_mask = BIT(0),
2253 .halt_reg = 0x33e4,
2255 .enable_reg = 0x33e4,
2256 .enable_mask = BIT(0),
2270 .halt_reg = 0x3414,
2272 .enable_reg = 0x3414,
2273 .enable_mask = BIT(0),
2287 .halt_reg = 0x3344,
2289 .enable_reg = 0x3344,
2290 .enable_mask = BIT(0),
2304 .halt_reg = 0x3348,
2306 .enable_reg = 0x3348,
2307 .enable_mask = BIT(0),
2321 .halt_reg = 0x3024,
2323 .enable_reg = 0x3024,
2324 .enable_mask = BIT(0),
2338 .halt_reg = 0x3054,
2340 .enable_reg = 0x3054,
2341 .enable_mask = BIT(0),
2355 .halt_reg = 0x3084,
2357 .enable_reg = 0x3084,
2358 .enable_mask = BIT(0),
2372 .halt_reg = 0x3234,
2374 .enable_reg = 0x3234,
2375 .enable_mask = BIT(0),
2389 .halt_reg = 0x3254,
2391 .enable_reg = 0x3254,
2392 .enable_mask = BIT(0),
2406 .halt_reg = 0x3274,
2408 .enable_reg = 0x3274,
2409 .enable_mask = BIT(0),
2423 .halt_reg = 0x35a8,
2425 .enable_reg = 0x35a8,
2426 .enable_mask = BIT(0),
2440 .halt_reg = 0x35b0,
2442 .enable_reg = 0x35b0,
2443 .enable_mask = BIT(0),
2457 .halt_reg = 0x35c0,
2459 .enable_reg = 0x35c0,
2460 .enable_mask = BIT(0),
2474 .halt_reg = 0x35b4,
2476 .enable_reg = 0x35b4,
2477 .enable_mask = BIT(0),
2491 .halt_reg = 0x35b8,
2493 .enable_reg = 0x35b8,
2494 .enable_mask = BIT(0),
2508 .halt_reg = 0x36b8,
2510 .enable_reg = 0x36b8,
2511 .enable_mask = BIT(0),
2525 .halt_reg = 0x36bc,
2527 .enable_reg = 0x36bc,
2528 .enable_mask = BIT(0),
2542 .halt_reg = 0x36a8,
2544 .enable_reg = 0x36a8,
2545 .enable_mask = BIT(0),
2559 .halt_reg = 0x3720,
2561 .enable_reg = 0x3720,
2562 .enable_mask = BIT(0),
2576 .halt_reg = 0x3668,
2578 .enable_reg = 0x3668,
2579 .enable_mask = BIT(0),
2593 .halt_reg = 0x36ac,
2595 .enable_reg = 0x36ac,
2596 .enable_mask = BIT(0),
2610 .halt_reg = 0x3724,
2612 .enable_reg = 0x3724,
2613 .enable_mask = BIT(0),
2627 .halt_reg = 0x3678,
2629 .enable_reg = 0x3678,
2630 .enable_mask = BIT(0),
2644 .halt_reg = 0x3704,
2646 .enable_reg = 0x3704,
2647 .enable_mask = BIT(0),
2661 .halt_reg = 0x3714,
2663 .enable_reg = 0x3714,
2664 .enable_mask = BIT(0),
2678 .halt_reg = 0x36c8,
2680 .enable_reg = 0x36c8,
2681 .enable_mask = BIT(0),
2695 .halt_reg = 0x36c4,
2697 .enable_reg = 0x36c4,
2698 .enable_mask = BIT(0),
2712 .halt_reg = 0x36b0,
2714 .enable_reg = 0x36b0,
2715 .enable_mask = BIT(0),
2729 .halt_reg = 0x36b4,
2731 .enable_reg = 0x36b4,
2732 .enable_mask = BIT(0),
2746 .halt_reg = 0x30b4,
2748 .enable_reg = 0x30b4,
2749 .enable_mask = BIT(0),
2763 .halt_reg = 0x30bc,
2765 .enable_reg = 0x30bc,
2766 .enable_mask = BIT(0),
2780 .halt_reg = 0x30c4,
2782 .enable_reg = 0x30c4,
2783 .enable_mask = BIT(0),
2797 .halt_reg = 0x30d4,
2799 .enable_reg = 0x30d4,
2800 .enable_mask = BIT(0),
2814 .halt_reg = 0x30e4,
2816 .enable_reg = 0x30e4,
2817 .enable_mask = BIT(0),
2831 .halt_reg = 0x3124,
2833 .enable_reg = 0x3124,
2834 .enable_mask = BIT(0),
2848 .halt_reg = 0x3128,
2850 .enable_reg = 0x3128,
2851 .enable_mask = BIT(0),
2865 .halt_reg = 0x3134,
2867 .enable_reg = 0x3134,
2868 .enable_mask = BIT(0),
2882 .halt_reg = 0x3144,
2884 .enable_reg = 0x3144,
2885 .enable_mask = BIT(0),
2899 .halt_reg = 0x3154,
2901 .enable_reg = 0x3154,
2902 .enable_mask = BIT(0),
2916 .halt_reg = 0x3184,
2918 .enable_reg = 0x3184,
2919 .enable_mask = BIT(0),
2933 .halt_reg = 0x3188,
2935 .enable_reg = 0x3188,
2936 .enable_mask = BIT(0),
2950 .halt_reg = 0x3194,
2952 .enable_reg = 0x3194,
2953 .enable_mask = BIT(0),
2967 .halt_reg = 0x31a4,
2969 .enable_reg = 0x31a4,
2970 .enable_mask = BIT(0),
2984 .halt_reg = 0x31b4,
2986 .enable_reg = 0x31b4,
2987 .enable_mask = BIT(0),
3001 .halt_reg = 0x31e4,
3003 .enable_reg = 0x31e4,
3004 .enable_mask = BIT(0),
3018 .halt_reg = 0x31e8,
3020 .enable_reg = 0x31e8,
3021 .enable_mask = BIT(0),
3035 .halt_reg = 0x31f4,
3037 .enable_reg = 0x31f4,
3038 .enable_mask = BIT(0),
3052 .halt_reg = 0x3204,
3054 .enable_reg = 0x3204,
3055 .enable_mask = BIT(0),
3069 .halt_reg = 0x3214,
3071 .enable_reg = 0x3214,
3072 .enable_mask = BIT(0),
3086 .halt_reg = 0x3224,
3088 .enable_reg = 0x3224,
3089 .enable_mask = BIT(0),
3103 .halt_reg = 0x3b68,
3105 .enable_reg = 0x3b68,
3106 .enable_mask = BIT(0),
3120 .halt_reg = 0x3b6c,
3122 .enable_reg = 0x3b6c,
3123 .enable_mask = BIT(0),
3137 .halt_reg = 0x3ba74,
3139 .enable_reg = 0x3ba74,
3140 .enable_mask = BIT(0),
3158 .gdscr = 0x529c,
3167 .gdscr = 0x119c,
3168 .gds_hw_ctrl = 0x120c,
3177 .gdscr = 0x247c,
3178 .gds_hw_ctrl = 0x2480,
3187 .gdscr = 0x3c4c,
3188 .gds_hw_ctrl = 0x3c50,
3197 .gdscr = 0x1024,
3198 .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 },
3208 .gdscr = 0x1040,
3209 .cxcs = (unsigned int []){ 0x1048 },
3220 .gdscr = 0x1044,
3221 .cxcs = (unsigned int []){ 0x104c },
3232 .gdscr = 0x34a0,
3233 .cxcs = (unsigned int []){ 0x36bc, 0x36c4 },
3243 .gdscr = 0x3664,
3244 .cxcs = (unsigned int []){ 0x36a8 },
3254 .gdscr = 0x3674,
3255 .cxcs = (unsigned int []){ 0x36ac },
3265 .gdscr = 0x35a4,
3266 .cxcs = (unsigned int []){ 0x35a8, 0x35b0, 0x35c0, 0x35b8 },
3276 .gdscr = 0x36d4,
3277 .cxcs = (unsigned int []){ 0x36b0 },
3287 .gdscr = 0x3b64,
3288 .cxcs = (unsigned int []){ 0x3b68, 0x3b6c },
3298 .gdscr = 0x2304,
3299 .cxcs = (unsigned int []){ 0x2310, 0x231c },
3309 .gdscr = 0x4034,
3310 .gds_hw_ctrl = 0x4038,
3319 .gdscr = 0x4024,
3320 .clamp_io_ctrl = 0x4300,
3321 .cxcs = (unsigned int []){ 0x4028 },
3526 [MMAGICAHB_BCR] = { 0x5020 },
3527 [MMAGIC_CFG_BCR] = { 0x5050 },
3528 [MISC_BCR] = { 0x5010 },
3529 [BTO_BCR] = { 0x5030 },
3530 [MMAGICAXI_BCR] = { 0x5060 },
3531 [MMAGICMAXI_BCR] = { 0x5070 },
3532 [DSA_BCR] = { 0x50a0 },
3533 [MMAGIC_CAMSS_BCR] = { 0x3c40 },
3534 [THROTTLE_CAMSS_BCR] = { 0x3c30 },
3535 [SMMU_VFE_BCR] = { 0x3c00 },
3536 [SMMU_CPP_BCR] = { 0x3c10 },
3537 [SMMU_JPEG_BCR] = { 0x3c20 },
3538 [MMAGIC_MDSS_BCR] = { 0x2470 },
3539 [THROTTLE_MDSS_BCR] = { 0x2460 },
3540 [SMMU_ROT_BCR] = { 0x2440 },
3541 [SMMU_MDP_BCR] = { 0x2450 },
3542 [MMAGIC_VIDEO_BCR] = { 0x1190 },
3543 [THROTTLE_VIDEO_BCR] = { 0x1180 },
3544 [SMMU_VIDEO_BCR] = { 0x1170 },
3545 [MMAGIC_BIMC_BCR] = { 0x5290 },
3546 [GPU_GX_BCR] = { 0x4020 },
3547 [GPU_BCR] = { 0x4030 },
3548 [GPU_AON_BCR] = { 0x4040 },
3549 [VMEM_BCR] = { 0x1200 },
3550 [MMSS_RBCPR_BCR] = { 0x4080 },
3551 [VIDEO_BCR] = { 0x1020 },
3552 [MDSS_BCR] = { 0x2300 },
3553 [CAMSS_TOP_BCR] = { 0x3480 },
3554 [CAMSS_AHB_BCR] = { 0x3488 },
3555 [CAMSS_MICRO_BCR] = { 0x3490 },
3556 [CAMSS_CCI_BCR] = { 0x3340 },
3557 [CAMSS_PHY0_BCR] = { 0x3020 },
3558 [CAMSS_PHY1_BCR] = { 0x3050 },
3559 [CAMSS_PHY2_BCR] = { 0x3080 },
3560 [CAMSS_CSIPHY0_3P_BCR] = { 0x3230 },
3561 [CAMSS_CSIPHY1_3P_BCR] = { 0x3250 },
3562 [CAMSS_CSIPHY2_3P_BCR] = { 0x3270 },
3563 [CAMSS_JPEG_BCR] = { 0x35a0 },
3564 [CAMSS_VFE_BCR] = { 0x36a0 },
3565 [CAMSS_VFE0_BCR] = { 0x3660 },
3566 [CAMSS_VFE1_BCR] = { 0x3670 },
3567 [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
3568 [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
3569 [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
3570 [CAMSS_CPP_BCR] = { 0x36d0 },
3571 [CAMSS_CSI0_BCR] = { 0x30b0 },
3572 [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
3573 [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
3574 [CAMSS_CSI1_BCR] = { 0x3120 },
3575 [CAMSS_CSI1RDI_BCR] = { 0x3140 },
3576 [CAMSS_CSI1PIX_BCR] = { 0x3150 },
3577 [CAMSS_CSI2_BCR] = { 0x3180 },
3578 [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
3579 [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
3580 [CAMSS_CSI3_BCR] = { 0x31e0 },
3581 [CAMSS_CSI3RDI_BCR] = { 0x3200 },
3582 [CAMSS_CSI3PIX_BCR] = { 0x3210 },
3583 [CAMSS_ISPIF_BCR] = { 0x3220 },
3584 [FD_BCR] = { 0x3b60 },
3585 [MMSS_SPDM_RM_BCR] = { 0x300 },
3592 .max_register = 0xb008,
3623 regmap_update_bits(regmap, 0x50d8, BIT(31), 0);
3625 regmap_update_bits(regmap, 0x5054, BIT(15), 0);