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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Driscv,aplic.yaml74 first child APLIC domain assigned child index 0. The APLIC domain child
122 reg = <0xc000000 0x4080>;
134 reg = <0xd000000 0x4080>;
144 reg = <0xe000000 0x4080>;
156 reg = <0xc000000 0x4000>;
167 reg = <0xd000000 0x4000>;
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dwasp_reg_map.h20 volatile char pad__0[0x4000]; /* 0x0 - 0x4000 */
21 volatile u_int32_t HOST_INTF_RESET_CONTROL; /* 0x4000 - 0x4004 */
22 volatile u_int32_t HOST_INTF_PM_CTRL; /* 0x4004 - 0x4008 */
23 volatile u_int32_t HOST_INTF_TIMEOUT; /* 0x4008 - 0x400c */
24 volatile u_int32_t HOST_INTF_SREV; /* 0x400c - 0x4010 */
25 volatile u_int32_t HOST_INTF_INTR_SYNC_CAUSE; /* 0x4010 - 0x4014 */
26 volatile u_int32_t HOST_INTF_INTR_SYNC_ENABLE; /* 0x4014 - 0x4018 */
27 volatile u_int32_t HOST_INTF_INTR_ASYNC_MASK; /* 0x4018 - 0x401c */
28 volatile u_int32_t HOST_INTF_INTR_SYNC_MASK; /* 0x401c - 0x4020 */
29 volatile u_int32_t HOST_INTF_INTR_ASYNC_CAUSE; /* 0x4020 - 0x4024 */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/ti/
H A Dti,am654-serdes-ctrl.yaml36 reg = <0x4080 0x4>;
41 mux-reg-masks = <0x0 0x3>; /* lane select */
H A Dti,j721e-system-controller.yaml48 "^mux-controller@[0-9a-f]+$":
53 "^clock-controller@[0-9a-f]+$":
59 "phy@[0-9a-f]+$":
65 "^chipid@[0-9a-f]+$":
84 reg = <0x00100000 0x1c000>;
91 reg = <0x00004080 0x50>;
95 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
96 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
97 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
98 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dti,j721e-system-controller.yaml48 "^mux-controller@[0-9a-f]+$":
53 "^clock-controller@[0-9a-f]+$":
59 "phy@[0-9a-f]+$":
65 "^chipid@[0-9a-f]+$":
84 reg = <0x00100000 0x1c000>;
91 reg = <0x00004080 0x50>;
95 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
96 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
97 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
98 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Damlogic-t7.dtsi16 #address-cells = <0x2>;
17 #size-cells = <0x0>;
54 reg = <0x0 0x100>;
61 reg = <0x0 0x101>;
68 reg = <0x0 0x102>;
75 reg = <0x0 0x103>;
79 cpu0: cpu@0 {
82 reg = <0x0 0x0>;
89 reg = <0x0 0x1>;
96 reg = <0x0 0x2>;
[all …]
H A Damlogic-c3.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
53 #clock-cells = <0>;
67 reg = <0x0 0x07f50e00 0x0 0x100>;
70 ranges = <0 0x0 0x07f50e00 0x100>;
72 scmi_shmem: sram@0 {
74 reg = <0x0 0x100>;
81 arm,smc-id = <0x820000C1>;
[all …]
H A Dmeson-s4.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0x0 0x0>;
30 reg = <0x0 0x1>;
37 reg = <0x0 0x2>;
44 reg = <0x0 0x3>;
66 #clock-cells = <0>;
89 #address-cells = <0>;
91 reg = <0x0 0xfff01000 0 0x1000>,
92 <0x0 0xfff02000 0 0x2000>,
[all …]
/freebsd/contrib/ofed/libcxgb4/
H A Dt4_pci_id_tbl.h46 * -- The PCI Function Number to use in the PCI Device ID Table. "0"
73 /* T4 and later ASICs use a PCI Device ID scheme of 0xVFPP where:
76 * F = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs
96 CH_PCI_ID_TABLE_FENTRY(0x4000), /* T440-dbg */
97 CH_PCI_ID_TABLE_FENTRY(0x4001), /* T420-cr */
98 CH_PCI_ID_TABLE_FENTRY(0x4002), /* T422-cr */
99 CH_PCI_ID_TABLE_FENTRY(0x4003), /* T440-cr */
100 CH_PCI_ID_TABLE_FENTRY(0x4004), /* T420-bch */
101 CH_PCI_ID_TABLE_FENTRY(0x400
[all...]
/freebsd/sys/dev/ntb/ntb_hw/
H A Dntb_hw_intel.h42 * Params: [in] P = Bit position of start of the bit field (lsb is 0).
51 #define NTB_LINK_STATUS_ACTIVE 0x2000
52 #define NTB_LINK_SPEED_MASK 0x000f
53 #define NTB_LINK_WIDTH_MASK 0x03f0
67 #define XEON_SPCICMD_OFFSET 0x0504
68 #define XEON_DEVCTRL_OFFSET 0x0598
69 #define XEON_DEVSTS_OFFSET 0x059a
70 #define XEON_LINK_STATUS_OFFSET 0x01a2
71 #define XEON_SLINK_STATUS_OFFSET 0x05a2
73 #define XEON_PBAR2LMT_OFFSET 0x0000
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j722s-main.dtsi12 serdes_refclk: clk-0 {
14 #clock-cells = <0>;
15 clock-frequency = <0>;
22 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
26 clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
37 reg = <0x0f000000 0x00010000>;
39 resets = <&serdes_wiz0 0>;
51 #size-cells = <0>;
60 ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
64 clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/mxs/
H A Dimx28-pinfunc.h13 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000
14 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010
15 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020
16 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030
17 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040
18 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050
19 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060
20 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070
21 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
22 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
[all …]
/freebsd/sys/arm/mv/
H A Dmvwin.h45 * SoC Integrated devices: 0xF1000000, 16 MB (VA == PA)
49 #define MV_PHYS_BASE 0xF1000000
53 #define MV_CESA_SRAM_BASE 0xF1100000
56 * External devices: 0x80000000, 1 GB (VA == PA)
62 #define MV_PCI_MEM_PHYS_BASE 0x80000000
67 #define MV_PCI_IO_PHYS_BASE 0xBF000000
71 #define MV_PCI_VA_MEM_BASE 0
72 #define MV_PCI_VA_IO_BASE 0
77 #define MV_DEV_BOOT_BASE 0xF9300000
80 #define MV_DEV_CS0_BASE 0xF9400000
[all …]
/freebsd/sys/i386/i386/
H A Delan-mmcr.c85 { 0xf0000, 0xf1000 },
87 { "Soekris", 0, 8 }, /* Soekris Engineering. */
88 { "net4", 0, 8 }, /* net45xx */
89 { "comBIOS", 0, 54 }, /* comBIOS ver. 1.26a 20040819 ... */
90 { NULL, 0, 0 },
105 v = u & 0xffff; in gpio_led()
108 v ^= 0xc; in gpio_led()
122 if (error != 0 || req->newptr == NULL) in sysctl_machdep_elan_gpio_config()
127 if (error != 0) in sysctl_machdep_elan_gpio_config()
130 np = ne = 0; in sysctl_machdep_elan_gpio_config()
[all …]
/freebsd/contrib/elftoolchain/libdwarf/
H A Ddwarf.h32 #define DW_TAG_array_type 0x01
33 #define DW_TAG_class_type 0x02
34 #define DW_TAG_entry_point 0x03
35 #define DW_TAG_enumeration_type 0x04
36 #define DW_TAG_formal_parameter 0x05
37 #define DW_TAG_imported_declaration 0x08
38 #define DW_TAG_label 0x0a
39 #define DW_TAG_lexical_block 0x0b
40 #define DW_TAG_member 0x0d
41 #define DW_TAG_pointer_type 0x0f
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/westmereep-dp/
H A Dmemory.json4 "Counter": "0,1,2,3",
5 "EventCode": "0x5",
8 "UMask": "0x2"
12 "Counter": "0,1,2,3",
13 "EventCode": "0xB7, 0xBB",
15 "MSRIndex": "0x1a6,0x1a7",
16 "MSRValue": "0x3011",
19 "UMask": "0x1"
23 "Counter": "0,1,2,3",
24 "EventCode": "0xB7, 0xBB",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/westmereep-sp/
H A Dmemory.json4 "Counter": "0,1,2,3",
5 "EventCode": "0xB7, 0xBB",
7 "MSRIndex": "0x1a6,0x1a7",
8 "MSRValue": "0x6011",
11 "UMask": "0x1"
15 "Counter": "0,1,2,3",
16 "EventCode": "0xB7, 0xBB",
18 "MSRIndex": "0x1a6,0x1a7",
19 "MSRValue": "0xF811",
22 "UMask": "0x1"
[all …]
/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2838_pci.c55 #define PCI_ID_VAL3 0x43c
56 #define CLASS_SHIFT 0x10
57 #define SUBCLASS_SHIFT 0x8
59 #define REG_CONTROLLER_HW_REV 0x406c
60 #define REG_BRIDGE_CTRL 0x9210
61 #define BRIDGE_DISABLE_FLAG 0x1
62 #define BRIDGE_RESET_FLAG 0x2
63 #define REG_PCIE_HARD_DEBUG 0x4204
64 #define REG_DMA_CONFIG 0x4008
65 #define REG_DMA_WINDOW_LOW 0x4034
[all …]
/freebsd/sys/arm64/apple/
H A Dapple_aic.c58 #define AIC_INFO 0x0004
59 #define AIC_INFO_NDIE(val) (((val) >> 24) & 0xf)
60 #define AIC_INFO_NIRQS(val) ((val) & 0x0000ffff)
62 #define AIC_WHOAMI 0x2000
63 #define AIC_EVENT 0x2004
64 #define AIC_EVENT_DIE(val) (((val) >> 24) & 0xff)
65 #define AIC_EVENT_TYPE(val) (((val) >> 16) & 0xff)
66 #define AIC_EVENT_TYPE_NONE 0
69 #define AIC_EVENT_IRQ(val) ((val) & 0xffff)
72 #define AIC_IPI_SEND 0x2008
[all …]
/freebsd/contrib/gdtoa/
H A Dgdtoaimp.h80 * for 0 <= k <= 22).
148 * preceded by 0x or 0X) and spaces; if there is only one string
160 * by FREE_DTOA_LOCK(n) for n = 0 or 1. (The second lock, accessed
270 #define Scale_Bit 0x10
298 #define word1(x) (x)->L[0]
300 #define word0(x) (x)->L[0]
307 * #define Storeinc(a,b,c) (*a++ = b << 16 | c & 0xffff)
311 ((unsigned short *)a)[0] = (unsigned short)c, a++)
313 #define Storeinc(a,b,c) (((unsigned short *)a)[0] = (unsigned short)b, \
326 #define Exp_msk1 0x100000
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUMCCodeEmitter.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
107 // immediate value, or 0 if it is not.
110 if (Imm >= 0 && Imm <= 64) in getIntInlineImmEncoding()
116 return 0; in getIntInlineImmEncoding()
121 if (IntImm != 0) in getLit16Encoding()
124 if (Val == 0x3800) // 0.5 in getLit16Encoding()
127 if (Val == 0xB800) // -0.5 in getLit16Encoding()
130 if (Val == 0x3C00) // 1.0 in getLit16Encoding()
133 if (Val == 0xBC00) // -1.0 in getLit16Encoding()
136 if (Val == 0x4000) // 2.0 in getLit16Encoding()
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5416/
H A Dar5416reg.h27 #define AR_MIRT 0x0020 /* interrupt rate threshold */
28 #define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */
29 #define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */
30 #define AR_GTXTO 0x0064 /* global transmit timeout */
31 #define AR_GTTM 0x0068 /* global transmit timeout mode */
32 #define AR_CST 0x006C /* carrier sense timeout */
33 #define AR_MAC_LED 0x1f04 /* LED control */
34 #define AR_WA 0x4004 /* PCIE work-arounds */
35 #define AR_PCIE_PM_CTRL 0x4014
36 #define AR_AHB_MODE 0x4024 /* AHB mode for dma */
[all …]
/freebsd/sys/arm64/freescale/imx/
H A Dimx8mp_ccm.c350 FIXED(IMX8MP_CLK_DUMMY, "dummy", 0),
359 MUX(IMX8MP_AUDIO_PLL1_REF_SEL, "audio_pll1_ref_sel", pll_ref_p, 0, 0x00, 0, 2),
360 MUX(IMX8MP_AUDIO_PLL2_REF_SEL, "audio_pll2_ref_sel", pll_ref_p, 0, 0x14, 0, 2),
361 MUX(IMX8MP_VIDEO_PLL1_REF_SEL, "video_pll1_ref_sel", pll_ref_p, 0, 0x28, 0, 2),
362 MUX(IMX8MP_DRAM_PLL_REF_SEL, "dram_pll_ref_sel", pll_ref_p, 0, 0x50, 0, 2),
363 MUX(IMX8MP_GPU_PLL_REF_SEL, "gpu_pll_ref_sel", pll_ref_p, 0, 0x64, 0, 2),
364 MUX(IMX8MP_VPU_PLL_REF_SEL, "vpu_pll_ref_sel", pll_ref_p, 0, 0x74, 0, 2),
365 MUX(IMX8MP_ARM_PLL_REF_SEL, "arm_pll_ref_sel", pll_ref_p, 0, 0x84, 0, 2),
366 MUX(IMX8MP_SYS_PLL1_REF_SEL, "sys_pll1_ref_sel", pll_ref_p, 0, 0x94, 0, 2),
367 MUX(IMX8MP_SYS_PLL2_REF_SEL, "sys_pll2_ref_sel", pll_ref_p, 0, 0x104, 0, 2),
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Drtw8922a.c26 {2, 1641, grp_0}, /* ACH 0 */
38 {0, 0, 0}, /* FWCMDQ */
39 {0, 0, 0}, /* BMC */
40 {0, 0, 0}, /* H2D */
44 1651, /* Group 0 */
47 0, /* WP threshold */
166 .ref_rate = {R_BE_TRXPTCL_RESP_1, B_BE_WMAC_RESP_REF_RATE_SEL, 0},
173 0xf},
176 0x0},
227 [RTW89_EFUSE_BLOCK_SYS] = {.offset = 0x00000, .size = 0x310},
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/
H A DDwarf.h3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
47 DW_TAG_invalid = ~0U, ///< Tag for invalid results.
48 DW_VIRTUALITY_invalid = ~0U, ///< Virtuality for invalid results.
49 DW_MACINFO_invalid = ~0U, ///< Macinfo type for invalid results.
54 DW_LENGTH_lo_reserved = 0xfffffff0, ///< Lower bound of the reserved range.
55 DW_LENGTH_DWARF64 = 0xffffffff, ///< Indicator of 64-bit DWARF format.
56 DW_LENGTH_hi_reserved = 0xffffffff, ///< Upper bound of the reserved range.
69 DWARF_VENDOR_DWARF = 0, ///< Defined in v2 or later of the DWARF standard.
106 DW_TAG_lo_user = 0x4080,
107 DW_TAG_hi_user = 0xffff,
[all …]

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